+@cocotb.test()
+def test04_shiftreg(dut):
+ """
+ Test of custom shiftreg
+ """
+ data_in = BinaryValue()
+ cmd_SR = BinaryValue("011")
+
+ # Run @ 1MHz
+ clk_period = get_sim_steps(1, "us")
+ master = JTAG_Master(
+ dut.tap_bus__tck, dut.tap_bus__tms, dut.tap_bus__tdi, dut.tap_bus__tdo,
+ clk_period=clk_period, ir_width=3,
+ )
+
+
+ dut._log.info("Load custom shiftreg command")
+ yield master.load_ir(cmd_SR)
+
+ data_in.binstr = "010"
+ dut._log.info(" input: {}".format(data_in.binstr))
+ yield master.shift_data(data_in)
+ dut._log.info(" output: {}".format(master.result.binstr))
+
+ data_in.binstr = "101"
+ dut._log.info(" input: {}".format(data_in.binstr))
+ yield master.shift_data(data_in)
+ dut._log.info(" output: {}".format(master.result.binstr))
+ assert master.result.binstr == "010"
+
+@cocotb.test()
+def test05_wishbone(dut):
+ """
+ Test of an added Wishbone interface
+ """
+ data_in = BinaryValue()
+ cmd_MEMADDRESS = BinaryValue("100")
+ cmd_MEMREAD = BinaryValue("101")
+ cmd_MEMREADWRITE = BinaryValue("110")
+
+ # Run JTAG @ 1MHz
+ jtagclk_period = get_sim_steps(1, "us")
+ master = JTAG_Master(
+ dut.tap_bus__tck, dut.tap_bus__tms, dut.tap_bus__tdi, dut.tap_bus__tdo,
+ clk_period=jtagclk_period, ir_width=3,
+ )
+ # Run main chip @ 10MHz; need to be clocked for Wishbone interface to function
+ cocotb.fork(Clock(dut.clk, 100, "ns").start())
+
+ # Add Wishbone memory on the bus
+ bus = WishboneBus(
+ entity=dut.tap, name="wb0", bus_separator="__", clock=dut.clk, reset=dut.rst,
+ signals={"datwr": "dat_w", "datrd": "dat_r"},
+ )
+ wbmem = WishboneMemory(bus)
+ cocotb.fork(wbmem.start())
+
+ # Load the memory address
+ yield master.load_ir(cmd_MEMADDRESS)
+ dut._log.info("Loading address")
+
+ data_in.binstr = "1100000000000000"
+ dut._log.info(" input: {}".format(data_in.binstr))
+ yield master.shift_data(data_in)
+ dut._log.info(" output: {}".format(master.result.binstr))
+
+ # Do write
+ yield master.load_ir(cmd_MEMREADWRITE)
+ dut._log.info("Writing memory")
+
+ data_in.binstr = "01010101"
+ dut._log.info(" input: {}".format(data_in.binstr))
+ yield master.shift_data(data_in)
+ dut._log.info(" output: {}".format(master.result.binstr))
+
+ data_in.binstr = "10101010"
+ dut._log.info(" input: {}".format(data_in.binstr))
+ yield master.shift_data(data_in)
+ dut._log.info(" output: {}".format(master.result.binstr))
+
+ # Load the memory address
+ yield master.load_ir(cmd_MEMADDRESS)
+ dut._log.info("Loading address")
+
+ data_in.binstr = "1100000000000000"
+ dut._log.info(" input: {}".format(data_in.binstr))
+ yield master.shift_data(data_in)
+ dut._log.info(" output: {}".format(master.result.binstr))
+ assert master.result.binstr == "1100000000000010"
+
+ # Do read and write
+ yield master.load_ir(cmd_MEMREADWRITE)
+ dut._log.info("Reading and writing memory")
+
+ data_in.binstr = "10101010"
+ dut._log.info(" input: {}".format(data_in.binstr))
+ yield master.shift_data(data_in)
+ dut._log.info(" output: {}".format(master.result.binstr))
+ assert master.result.binstr == "01010101"
+
+ data_in.binstr = "01010101"
+ dut._log.info(" input: {}".format(data_in.binstr))
+ yield master.shift_data(data_in)
+ dut._log.info(" output: {}".format(master.result.binstr))
+ assert master.result.binstr == "10101010"
+
+ # Load the memory address
+ yield master.load_ir(cmd_MEMADDRESS)
+ dut._log.info("Loading address")
+
+ data_in.binstr = "1100000000000000"
+ dut._log.info(" input: {}".format(data_in.binstr))
+ yield master.shift_data(data_in)
+ dut._log.info(" output: {}".format(master.result.binstr))
+ assert master.result.binstr == "1100000000000010"
+
+ # Do read
+ yield master.load_ir(cmd_MEMREAD)
+ dut._log.info("Reading memory")
+ data_in.binstr = "00000000"
+
+ dut._log.info(" input: {}".format(data_in.binstr))
+ yield master.shift_data(data_in)
+ dut._log.info(" output: {}".format(master.result.binstr))
+ assert master.result.binstr == "10101010"
+
+ dut._log.info(" input: {}".format(data_in.binstr))
+ yield master.shift_data(data_in)
+ dut._log.info(" output: {}".format(master.result.binstr))
+ assert master.result.binstr == "01010101"
+
+ # Load the memory address
+ yield master.load_ir(cmd_MEMADDRESS) # MEMADDR
+ dut._log.info("Loading address")
+
+ data_in.binstr = "1100000000000000"
+ dut._log.info(" input: {}".format(data_in.binstr))
+ yield master.shift_data(data_in)
+ dut._log.info(" output: {}".format(master.result.binstr))
+ assert master.result.binstr == "1100000000000010"
+
+ # Do read
+ yield master.load_ir(cmd_MEMREAD) # MEMREAD
+ dut._log.info("Reading memory")
+ data_in.binstr = "00000000"
+
+ dut._log.info(" input: {}".format(data_in.binstr))
+ yield master.shift_data(data_in)
+ dut._log.info(" output: {}".format(master.result.binstr))
+ assert master.result.binstr == "10101010"
+
+ dut._log.info(" input: {}".format(data_in.binstr))
+ yield master.shift_data(data_in)
+ dut._log.info(" output: {}".format(master.result.binstr))
+ assert master.result.binstr == "01010101"