X-Git-Url: https://git.libre-soc.org/?p=c4m-jtag.git;a=blobdiff_plain;f=c4m%2Fnmigen%2Fjtag%2Fbus.py;h=d1532bc08d0d8170c5b7c5e62dba67f8c6fe709a;hp=c6015a72657eb77b15d36afb0a440a37bd23e7e5;hb=6b2a90b3dddda411e096e577a9f7b35fe2492878;hpb=85d7ce239ef57731cc1dcb2c8ffc6ffc85f77a5d

diff --git a/c4m/nmigen/jtag/bus.py b/c4m/nmigen/jtag/bus.py
index c6015a7..d1532bc 100644
--- a/c4m/nmigen/jtag/bus.py
+++ b/c4m/nmigen/jtag/bus.py
@@ -1,6 +1,20 @@
 from nmigen import *
 from nmigen.hdl.rec import Direction
 
+
+class DMIInterface(Record):
+    def __init__(self, name=None, addr_wid=4, data_wid=64):
+        layout = [
+           ('addr_i', addr_wid, Direction.FANIN),  # DMI register address
+           ('din',    data_wid, Direction.FANIN),  # DMI data write in (we=1)
+           ('dout',   data_wid, Direction.FANOUT), # DMI data read out (we=0)
+           ('req_i',  1,        Direction.FANIN),  # DMI request valid (stb)
+           ('we_i',   1,        Direction.FANIN),  # DMI write-enable
+           ('ack_o',  1,        Direction.FANOUT), # DMI ack request
+        ]
+        super().__init__(name=name, layout=layout)
+
+
 class Interface(Record):
     """JTAG Interface.