X-Git-Url: https://git.libre-soc.org/?p=c4m-jtag.git;a=blobdiff_plain;f=c4m%2Fnmigen%2Fjtag%2Fjtag.py;h=0e4de64a43e03e646114301e3614fa27a2da7506;hp=88d12922149c87d5763dc2f9670edd656831d66d;hb=62a29aa5ee3116835b8795ffe9ec41e9d7683e21;hpb=8b498dec0d4ba382284e82ab69bb123df1f3c204;ds=sidebyside

diff --git a/c4m/nmigen/jtag/jtag.py b/c4m/nmigen/jtag/jtag.py
index 88d1292..0e4de64 100755
--- a/c4m/nmigen/jtag/jtag.py
+++ b/c4m/nmigen/jtag/jtag.py
@@ -8,53 +8,11 @@ from nmigen.lib.io import *
 from wishbone import Wishbone
 
 __all__ = [
-    "PmodJTAGMasterResource",
-    "PmodJTAGMasterAResource",
-    "PmodJTAGSlaveResource",
-    "PmodJTAGSlaveAResource",
     "JTAG",
 ]
 
 #TODO: Provide more documentation
 
-def PmodJTAGMasterResource(name, number, *, pmod, attrs=Attrs(IOSTANDARD="LVCMOS33")):
-    return Resource(name, number,
-        Subsignal("TCK", Pins("1", dir="o", conn=("pmod", pmod))),
-        Subsignal("TMS", Pins("2", dir="o", conn=("pmod", pmod))),
-        Subsignal("TDO", Pins("3", dir="o", conn=("pmod", pmod))),
-        Subsignal("TDI", Pins("4", dir="i", conn=("pmod", pmod))),
-        attrs,
-    )
-
-def PmodJTAGMasterAResource(name, number, *, pmod, attrs=Attrs(IOSTANDARD="LVCMOS33")):
-    return Resource(name, number,
-        Subsignal("TCK", Pins("1", dir="o", conn=("pmod", pmod))),
-        Subsignal("TMS", Pins("2", dir="o", conn=("pmod", pmod))),
-        Subsignal("TDO", Pins("3", dir="o", conn=("pmod", pmod))),
-        Subsignal("TDI", Pins("4", dir="i", conn=("pmod", pmod))),
-        Subsignal("TRST", PinsN("7", dir="o", conn=("pmod", pmod))),
-        attrs,
-    )
-
-def PmodJTAGSlaveResource(name, number, *, pmod, attrs=Attrs(IOSTANDARD="LVCMOS33")):
-    return Resource(name, number,
-        Subsignal("TCK", Pins("1", dir="i", conn=("pmod", pmod))),
-        Subsignal("TMS", Pins("2", dir="i", conn=("pmod", pmod))),
-        Subsignal("TDI", Pins("3", dir="i", conn=("pmod", pmod))),
-        Subsignal("TDO", Pins("4", dir="o", conn=("pmod", pmod))),
-        attrs,
-    )
-
-def PmodJTAGSlaveAResource(name, number, *, pmod, attrs=Attrs(IOSTANDARD="LVCMOS33")):
-    return Resource(name, number,
-        Subsignal("TCK", Pins("1", dir="i", conn=("pmod", pmod))),
-        Subsignal("TMS", Pins("2", dir="i", conn=("pmod", pmod))),
-        Subsignal("TDI", Pins("3", dir="i", conn=("pmod", pmod))),
-        Subsignal("TDO", Pins("4", dir="o", conn=("pmod", pmod))),
-        Subsignal("TRST", PinsN("7", dir="i", conn=("pmod", pmod))),
-        attrs,
-    )
-
 
 class ShiftReg(Elaboratable):
     def __init__(self, ircodes, length, domain):