X-Git-Url: https://git.libre-soc.org/?p=c4m-jtag.git;a=blobdiff_plain;f=test%2Fnmigen%2Fcocotb%2Fcontroller%2FMakefile;h=e19adeead15470c9da23bf457c5bf0f603078224;hp=1257cb2603b4e02f35a338b224f6b6d221828ae5;hb=4941742ce117f8d2a24e00eb6d76255ea8c99118;hpb=51a2c618ed83fd8c69120e885d17f2e108e44ed4

diff --git a/test/nmigen/cocotb/controller/Makefile b/test/nmigen/cocotb/controller/Makefile
index 1257cb2..e19adee 100644
--- a/test/nmigen/cocotb/controller/Makefile
+++ b/test/nmigen/cocotb/controller/Makefile
@@ -18,14 +18,6 @@ TOPVCD := $(CURDIR)/$(TOPLEVEL).vcd
 # COCOTB
 #
 VHDL_SOURCES = \
-  $(CODEDIR)/jtag/c4m_jtag_pkg.vhdl \
-  $(CODEDIR)/jtag/c4m_jtag_tap_fsm.vhdl \
-  $(CODEDIR)/jtag/c4m_jtag_irblock.vhdl \
-  $(CODEDIR)/jtag/c4m_jtag_iocell.vhdl \
-  $(CODEDIR)/jtag/c4m_jtag_ioblock.vhdl \
-  $(CODEDIR)/jtag/c4m_jtag_idblock.vhdl \
-  $(CODEDIR)/jtag/c4m_jtag_tap_controller.vhdl \
-  $(CODEDIR)/jtag/jtag_controller_i0.vhdl \
 #VHDL_SOURCES end
 VERILOG_SOURCES = \
   $(TOPFILE) \
@@ -77,4 +69,4 @@ $(TOPVCD): sim
 
 .PHONY: clean
 clean::
-	@rm -fr code $(TOPVCD)
+	@rm -fr code $(TOPVCD) __pycache__