+#!/usr/bin/env python3
#!/bin/env python3
+# Copyright (C) 2019,2020,2021 Staf Verhaegen <staf@fibraservi.eu>
+# Copyright (C) 2021,2022 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+# Funded by NLnet and NGI POINTER under EU Grants 871528 and 957073
+
import os, textwrap
from enum import Enum, auto
self.shift = Signal()
self.update = Signal()
+ # JTAG uses both edges of the incoming clock (TCK). set them up here
self.posjtag = ClockDomain("posjtag", local=True)
self.negjtag = ClockDomain("negjtag", local=True, clk_edge="neg")
return m
+
class _IRBlock(Elaboratable):
"""TAP subblock for handling the IR shift register"""
def __init__(self, *, ir_width, cmd_idcode,
return m
+
class IOType(Enum):
In = auto()
Out = auto()
TriOut = auto()
InTriOut = auto()
+
class IOConn(Record):
lengths = {
IOType.In: 1,
}
"""TAP subblock representing the interface for an JTAG IO cell.
- It contains signal to connect to the core and to the pad
+ It contains signals to connect to the core and to the pad
This object is normally only allocated and returned from ``TAP.add_io``
It is a Record subclass.
Input to pad with pad output value.
oe: Signal(1), present only for IOType.TriOut and IOType.InTriOut.
Input to pad with pad output enable value.
+
+ bank select, pullup and pulldown may also be optionally added
"""
@staticmethod
- def layout(iotype):
+ def layout(iotype, banksel=0, pullup=False, pulldown=False):
sigs = []
if iotype in (IOType.In, IOType.InTriOut):
sigs.append(("i", 1))
sigs.append(("o", 1))
if iotype in (IOType.TriOut, IOType.InTriOut):
sigs.append(("oe", 1))
+ if banksel > 0:
+ sigs.append(("sel", banksel))
+ if pullup:
+ sigs.append(("pu", 1))
+ if pulldown:
+ sigs.append(("pd", 1))
return Layout((("core", sigs), ("pad", sigs)))
- def __init__(self, *, iotype, name=None, src_loc_at=0):
- super().__init__(self.__class__.layout(iotype), name=name,
- src_loc_at=src_loc_at+1)
+ def __init__(self, *, iotype, name=None, banksel=0,
+ pullup=False, pulldown=False,
+ src_loc_at=0):
+ layout = self.__class__.layout(iotype, banksel, pullup, pulldown)
+ super().__init__(layout, name=name, src_loc_at=src_loc_at+1)
self._iotype = iotype
+ self._banksel = banksel
+ self._pullup = pullup
+ self._pulldown = pulldown
+
class _IDBypassBlock(Elaboratable):
"""TAP subblock for the ID shift register"""
]
super().__init__(layout, name=name, src_loc_at=src_loc_at+1)
+
class TAP(Elaboratable):
#TODO: Document TAP
def __init__(self, *, with_reset=False, ir_width=None,
cmd_preload = 2
cmd_bypass = 2**ir_width - 1 # All ones
- m.submodules._fsm = fsm = _FSM(bus=self.bus)
+ m.submodules.fsm = fsm = _FSM(bus=self.bus)
m.domains.posjtag = fsm.posjtag
m.domains.negjtag = fsm.negjtag
# IR block
select_ir = fsm.isir
- m.submodules._irblock = irblock = _IRBlock(
+ m.submodules.irblock = irblock = _IRBlock(
ir_width=ir_width, cmd_idcode=cmd_idcode, tdi=self.bus.tdi,
capture=(fsm.isir & fsm.capture),
shift=(fsm.isir & fsm.shift),
m.d.comb += select_id.eq(fsm.isdr &
((ir == cmd_idcode) | (ir == cmd_bypass)))
m.d.comb += id_bypass.eq(ir == cmd_bypass)
- m.submodules._idblock = idblock = _IDBypassBlock(
+ m.submodules.idblock = idblock = _IDBypassBlock(
manufacturer_id=self._manufacturer_id,
part_number=self._part_number,
version=self._version, tdi=self.bus.tdi,
m.d.comb += tdo.eq(irblock.tdo)
with m.Elif(select_id):
m.d.comb += tdo.eq(idblock.tdo)
- if io_tdo is not None:
- with m.Elif(select_io):
- m.d.comb += tdo.eq(io_tdo)
+ with m.Elif(select_io):
+ m.d.comb += tdo.eq(io_tdo)
# shiftregs block
self._elaborate_shiftregs(
dmi.we_i.eq(ds.ongoing("WRRD")),
]
- def add_io(self, *, iotype, name=None, src_loc_at=0):
+ def add_io(self, *, iotype, name=None, banksel=0,
+ pullup=False, pulldown=False,
+ src_loc_at=0):
"""Add a io cell to the boundary scan chain
Parameters:
if name is None:
name = "ioconn" + str(len(self._ios))
- ioconn = IOConn(iotype=iotype, name=name, src_loc_at=src_loc_at+1)
+ ioconn = IOConn(iotype=iotype, banksel=banksel,
+ pullup=pullup, pulldown=pulldown,
+ name=name, src_loc_at=src_loc_at+1)
self._ios.append(ioconn)
return ioconn
def _elaborate_ios(self, *, m, capture, shift, update, bd2io, bd2core):
- length = sum(IOConn.lengths[conn._iotype] for conn in self._ios)
+ # note: the starting points where each IOConn is placed into
+ # the Shift Register depends *specifically* on the type (parameters)
+ # of each IOConn, and therefore on all IOConn(s) that came before it
+ # [prior calls to add_io]. this function consistently follows
+ # the exact same pattern in the exact same sequence every time,
+ # to compute consistent offsets. developers must do the same:
+ # note that each length depends on *all* parameters:
+ # IOtype, banksel, pullup *and* pulldown.
+
+ # pre-compute the length of the IO shift registers needed.
+ length = 0
+ for conn in self._ios:
+ length += IOConn.lengths[conn._iotype] + conn._banksel
+ if conn._pullup:
+ length += 1
+ if conn._pulldown:
+ length += 1
if length == 0:
- return None
+ return self.bus.tdi
io_sr = Signal(length)
io_bd = Signal(length)
iol.append(conn.core.o)
if conn._iotype in [IOType.TriOut, IOType.InTriOut]:
iol.append(conn.core.oe)
- # length double-check
+ # now also banksel, pullup and pulldown from core are added
+ if conn._banksel != 0:
+ iol.append(conn.core.sel)
+ idx += conn._banksel
+ if conn._pullup:
+ iol.append(conn.core.pu)
+ idx += 1
+ if conn._pulldown:
+ iol.append(conn.core.pd)
+ idx += 1
+ # help with length double-check
idx += IOConn.lengths[conn._iotype] # fails if wrong type
- assert idx == length, "Internal error"
+ assert idx == length, "Internal error, length mismatch"
m.d.posjtag += io_sr.eq(Cat(*iol)) # assigns all io_sr in one hit
# "Shift" mode (sends out captured data on tdo, sets incoming from tdi)
# sets up IO (pad<->core) or in testing mode depending on requested
# mode, via Muxes controlled by bd2core and bd2io
+ # for each IOConn, the number of bits needed from io_bd will vary
+ # and is computed on-the-fly, here. it is up to the developer to
+ # keep track of where each IO pad configuration starts and ends
+ # in the Shift Register (TODO: provide a dictionary of starting points)
idx = 0
for conn in self._ios:
+ # mux the I/O/OE depending on IOType
if conn._iotype == IOType.In:
m.d.comb += conn.core.i.eq(Mux(bd2core, io_bd[idx], conn.pad.i))
idx += 1
idx += 3
else:
raise("Internal error")
+ # optional mux of banksel, pullup and pulldown. note that idx
+ # advances each time, so that io_bd[idx] comes from the right point
+ comb = m.d.comb
+ if conn._banksel != 0:
+ s, e = (idx, idx+conn._banksel) # banksel can be multi-bit
+ comb += conn.pad.sel.eq(Mux(bd2io, io_bd[s:e], conn.core.sel))
+ idx = e
+ if conn._pullup:
+ comb += conn.pad.pu.eq(Mux(bd2io, io_bd[idx], conn.core.pu))
+ idx += 1
+ if conn._pulldown:
+ comb += conn.pad.pd.eq(Mux(bd2io, io_bd[idx], conn.core.pd))
+ idx += 1
assert idx == length, "Internal error"
+ # return the last bit of the shift register, for output on tdo
return io_sr[-1]
def add_shiftreg(self, *, ircode, length, domain="sync", name=None,
# clockdomain latch update in `domain` clockdomain and see when
# it has falling edge.
# At that edge put isir in sr.oe for one `domain` clockdomain
+ # Using this custom sync <> JTAG domain synchronization avoids
+ # the use of more generic but also higher latency CDC solutions
+ # like FFSynchronizer.
update_core = Signal(name=sr.name+"_update_core")
update_core_prev = Signal(name=sr.name+"_update_core_prev")
m.d[domain] += [
# tdo = reg[0], tdo_en = shift
tdos.append((reg[0], sr_shift))
-
# Assign the right tdo to the bus tdo
for i, (tdo, tdo_en) in enumerate(tdos):
if i == 0:
# Always connect tdo_jtag to
m.d.comb += self.bus.tdo.eq(tdo_jtag)
-
def add_wishbone(self, *, ircodes, address_width, data_width,
granularity=None, domain="sync", features=None,
name=None, src_loc_at=0):
with m.State("READACK"):
with m.If(wb.ack):
# Store read data in sr_data.i
- # and keep it there til next read
+ # and keep it there til next read.
+ # This is enough to synchronize between sync and JTAG
+ # clock domain and no higher latency solutions like
+ # FFSynchronizer is needed.
m.d[domain] += sr_data.i.eq(wb.dat_r)
m.next = "IDLE"
with m.State("WRITEREAD"):
m.d[domain] += wb.adr.eq(wb.adr + 1)
m.next = "READ"
- m.d.comb += [
- wb.cyc.eq(~fsm.ongoing("IDLE")),
- wb.stb.eq(fsm.ongoing("READ") | fsm.ongoing("WRITEREAD")),
- wb.we.eq(fsm.ongoing("WRITEREAD")),
- ]
+ if hasattr(wb, "stall"):
+ m.d.comb += wb.stb.eq(fsm.ongoing("READ") |
+ fsm.ongoing("WRITEREAD"))
+ m.d.comb += wb.we.eq(fsm.ongoing("WRITEREAD"))
+ else:
+ # non-stall is single-cycle (litex), must assert stb
+ # until ack is sent
+ m.d.comb += wb.stb.eq(fsm.ongoing("READ") |
+ fsm.ongoing("WRITEREAD") |
+ fsm.ongoing("READACK") |
+ fsm.ongoing("WRITEREADACK"))
+ m.d.comb += wb.we.eq(fsm.ongoing("WRITEREAD") |
+ fsm.ongoing("WRITEREADACK"))
+ m.d.comb += wb.cyc.eq(~fsm.ongoing("IDLE"))
+++ /dev/null
-/* Generated by Yosys 0.9+932 (git sha1 ff8529a, gcc 4.8.5 -fPIC -Os) */
-
-(* generator = "nMigen" *)
-(* \nmigen.hierarchy = "top._fsm" *)
-module _fsm(tap_fsm_isdr, jtag_clk, tap_bus__tck, tap_bus__tms, tap_fsm_capture, tap_fsm_shift, tap_fsm_update, jtag_rst, tap_fsm_isir);
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:359" *)
- output jtag_clk;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:359" *)
- output jtag_rst;
- (* src = "./generate.py:16" *)
- input tap_bus__tck;
- (* src = "./generate.py:16" *)
- input tap_bus__tms;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:25" *)
- output tap_fsm_capture;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:24" *)
- output tap_fsm_isdr;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:23" *)
- output tap_fsm_isir;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:26" *)
- output tap_fsm_shift;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:27" *)
- output tap_fsm_update;
- c4m_jtag_tap_fsm inst (
- .capture(tap_fsm_capture),
- .isdr(tap_fsm_isdr),
- .isir(tap_fsm_isir),
- .reset(jtag_rst),
- .shift(tap_fsm_shift),
- .tck(tap_bus__tck),
- .tms(tap_bus__tms),
- .trst_n(1'h1),
- .update(tap_fsm_update)
- );
- assign jtag_clk = tap_bus__tck;
-endmodule
-
-(* generator = "nMigen" *)
-(* \nmigen.hierarchy = "top._idblock" *)
-module _idblock(ir, tap_id_tdo, jtag_clk, tap_fsm_capture, tap_fsm_shift, tap_bus__tdi, jtag_rst, tap_fsm_isdr);
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *)
- wire \$1 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:380" *)
- wire \$11 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:114" *)
- wire [31:0] \$13 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *)
- wire \$3 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:379" *)
- wire \$5 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *)
- wire \$7 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *)
- wire \$9 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:60" *)
- input [1:0] ir;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:359" *)
- input jtag_clk;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:359" *)
- input jtag_rst;
- (* src = "./generate.py:16" *)
- input tap_bus__tdi;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:25" *)
- input tap_fsm_capture;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:24" *)
- input tap_fsm_isdr;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:26" *)
- input tap_fsm_shift;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:107" *)
- reg [31:0] tap_id_sr = 32'd0;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:107" *)
- reg [31:0] \tap_id_sr$next ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:97" *)
- output tap_id_tdo;
- assign \$9 = tap_fsm_isdr & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *) \$7 ;
- assign \$11 = \$9 & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:380" *) tap_fsm_shift;
- assign \$13 = + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:114" *) { tap_bus__tdi, tap_id_sr[31:2] };
- assign \$1 = ir == (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *) 1'h1;
- assign \$3 = tap_fsm_isdr & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *) \$1 ;
- assign \$5 = \$3 & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:379" *) tap_fsm_capture;
- assign \$7 = ir == (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *) 1'h1;
- always @(posedge jtag_clk)
- tap_id_sr <= \tap_id_sr$next ;
- always @* begin
- \tap_id_sr$next = tap_id_sr;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:111" *)
- casez ({ \$11 , \$5 })
- /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:111" */
- 2'b?1:
- \tap_id_sr$next = 32'd6399;
- /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:113" */
- 2'b1?:
- \tap_id_sr$next = \$13 ;
- endcase
- end
- assign tap_id_tdo = tap_id_sr[0];
-endmodule
-
-(* generator = "nMigen" *)
-(* \nmigen.hierarchy = "top._ioblock" *)
-module _ioblock(tap_io_tdo, tap_fsm_capture, tap_fsm_shift, tap_fsm_update, tap_bus__tdi, clk, tap_coreio0__o, tap_coreio1__o, tap_coreio0__oe, tap_coreio1__oe, tap_padio0__i, tap_padio1__i, ir);
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ir.py:538" *)
- input clk;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:60" *)
- input [1:0] ir;
- (* src = "./generate.py:16" *)
- input tap_bus__tdi;
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *)
- wire tap_coreio0__i;
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *)
- input tap_coreio0__o;
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *)
- input tap_coreio0__oe;
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *)
- wire tap_coreio1__i;
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *)
- input tap_coreio1__o;
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *)
- input tap_coreio1__oe;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:25" *)
- input tap_fsm_capture;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:26" *)
- input tap_fsm_shift;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:27" *)
- input tap_fsm_update;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:194" *)
- output tap_io_tdo;
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *)
- input tap_padio0__i;
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *)
- wire tap_padio0__o;
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *)
- wire tap_padio0__oe;
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *)
- input tap_padio1__i;
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *)
- wire tap_padio1__o;
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *)
- wire tap_padio1__oe;
- jtag_ioblock_2_2 inst (
- .capture(tap_fsm_capture),
- .core_en({ tap_coreio1__oe, tap_coreio0__oe }),
- .core_in({ tap_coreio1__i, tap_coreio0__i }),
- .core_out({ tap_coreio1__o, tap_coreio0__o }),
- .ir(ir),
- .pad_en({ tap_padio1__oe, tap_padio0__oe }),
- .pad_in({ tap_padio1__i, tap_padio0__i }),
- .pad_out({ tap_padio1__o, tap_padio0__o }),
- .shift(tap_fsm_shift),
- .tck(clk),
- .tdi(tap_bus__tdi),
- .tdo(tap_io_tdo),
- .update(tap_fsm_update)
- );
-endmodule
-
-(* generator = "nMigen" *)
-(* \nmigen.hierarchy = "top._irblock" *)
-module _irblock(ir, tdo, jtag_clk, tap_fsm_capture, tap_fsm_shift, tap_fsm_update, tap_bus__tdi, jtag_rst, tap_fsm_isir);
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:368" *)
- wire \$1 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:369" *)
- wire \$11 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:370" *)
- wire \$13 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:369" *)
- wire \$3 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:370" *)
- wire \$5 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:77" *)
- wire [1:0] \$7 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:368" *)
- wire \$9 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:60" *)
- output [1:0] ir;
- reg [1:0] ir = 2'h1;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:60" *)
- reg [1:0] \ir$next ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:359" *)
- input jtag_clk;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:359" *)
- input jtag_rst;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:71" *)
- reg [1:0] shift_ir = 2'h0;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:71" *)
- reg [1:0] \shift_ir$next ;
- (* src = "./generate.py:16" *)
- input tap_bus__tdi;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:25" *)
- input tap_fsm_capture;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:23" *)
- input tap_fsm_isir;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:26" *)
- input tap_fsm_shift;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:27" *)
- input tap_fsm_update;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:61" *)
- output tdo;
- assign \$9 = tap_fsm_isir & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:368" *) tap_fsm_capture;
- assign \$11 = tap_fsm_isir & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:369" *) tap_fsm_shift;
- assign \$13 = tap_fsm_isir & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:370" *) tap_fsm_update;
- assign \$1 = tap_fsm_isir & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:368" *) tap_fsm_capture;
- assign \$3 = tap_fsm_isir & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:369" *) tap_fsm_shift;
- assign \$5 = tap_fsm_isir & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:370" *) tap_fsm_update;
- assign \$7 = + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:77" *) tap_bus__tdi;
- always @(posedge jtag_clk)
- ir <= \ir$next ;
- always @(posedge jtag_clk)
- shift_ir <= \shift_ir$next ;
- always @* begin
- \shift_ir$next = shift_ir;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:74" *)
- casez ({ \$5 , \$3 , \$1 })
- /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:74" */
- 3'b??1:
- \shift_ir$next = ir;
- /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:76" */
- 3'b?1?:
- \shift_ir$next = \$7 ;
- endcase
- end
- always @* begin
- \ir$next = ir;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:74" *)
- casez ({ \$13 , \$11 , \$9 })
- /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:74" */
- 3'b??1:
- /* empty */;
- /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:76" */
- 3'b?1?:
- /* empty */;
- /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:78" */
- 3'b1??:
- \ir$next = shift_ir;
- endcase
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/xfrm.py:528" *)
- casez (jtag_rst)
- 1'h1:
- \ir$next = 2'h1;
- endcase
- end
- assign tdo = ir[0];
-endmodule
-
-(* generator = "nMigen" *)
-(* top = 1 *)
-(* \nmigen.hierarchy = "top" *)
-module top(tap_bus__tms, tap_bus__tdi, clk, tap_coreio0__o, tap_coreio1__o, tap_coreio0__oe, tap_coreio1__oe, tap_padio0__i, tap_padio1__i, tap_bus__tck);
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *)
- wire \$1 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *)
- wire \$11 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *)
- wire \$13 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *)
- wire \$15 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *)
- wire \$3 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *)
- wire \$5 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *)
- wire \$7 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *)
- wire \$9 ;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:359" *)
- wire _fsm_jtag_clk;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:359" *)
- wire _fsm_jtag_rst;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:25" *)
- wire _fsm_tap_fsm_capture;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:24" *)
- wire _fsm_tap_fsm_isdr;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:23" *)
- wire _fsm_tap_fsm_isir;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:26" *)
- wire _fsm_tap_fsm_shift;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:27" *)
- wire _fsm_tap_fsm_update;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:97" *)
- wire _idblock_tap_id_tdo;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:194" *)
- wire _ioblock_tap_io_tdo;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:60" *)
- wire [1:0] _irblock_ir;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:61" *)
- wire _irblock_tdo;
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ir.py:538" *)
- input clk;
- (* src = "./generate.py:16" *)
- input tap_bus__tck;
- (* src = "./generate.py:16" *)
- input tap_bus__tdi;
- (* src = "./generate.py:16" *)
- wire tap_bus__tdo;
- (* src = "./generate.py:16" *)
- input tap_bus__tms;
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *)
- input tap_coreio0__o;
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *)
- input tap_coreio0__oe;
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *)
- input tap_coreio1__o;
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *)
- input tap_coreio1__oe;
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *)
- input tap_padio0__i;
- (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *)
- input tap_padio1__i;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:397" *)
- reg tap_tdo;
- assign \$9 = \$5 | (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *) \$7 ;
- assign \$11 = _irblock_ir == (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *) 2'h2;
- assign \$13 = \$9 | (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *) \$11 ;
- assign \$15 = _fsm_tap_fsm_isdr & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *) \$13 ;
- assign \$1 = _irblock_ir == (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *) 1'h1;
- assign \$3 = _fsm_tap_fsm_isdr & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *) \$1 ;
- assign \$5 = _irblock_ir == (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *) 1'h0;
- assign \$7 = _irblock_ir == (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *) 2'h2;
- _fsm _fsm (
- .jtag_clk(_fsm_jtag_clk),
- .jtag_rst(_fsm_jtag_rst),
- .tap_bus__tck(tap_bus__tck),
- .tap_bus__tms(tap_bus__tms),
- .tap_fsm_capture(_fsm_tap_fsm_capture),
- .tap_fsm_isdr(_fsm_tap_fsm_isdr),
- .tap_fsm_isir(_fsm_tap_fsm_isir),
- .tap_fsm_shift(_fsm_tap_fsm_shift),
- .tap_fsm_update(_fsm_tap_fsm_update)
- );
- _idblock _idblock (
- .ir(_irblock_ir),
- .jtag_clk(_fsm_jtag_clk),
- .jtag_rst(_fsm_jtag_rst),
- .tap_bus__tdi(tap_bus__tdi),
- .tap_fsm_capture(_fsm_tap_fsm_capture),
- .tap_fsm_isdr(_fsm_tap_fsm_isdr),
- .tap_fsm_shift(_fsm_tap_fsm_shift),
- .tap_id_tdo(_idblock_tap_id_tdo)
- );
- _ioblock _ioblock (
- .clk(clk),
- .ir(_irblock_ir),
- .tap_bus__tdi(tap_bus__tdi),
- .tap_coreio0__o(tap_coreio0__o),
- .tap_coreio0__oe(tap_coreio0__oe),
- .tap_coreio1__o(tap_coreio1__o),
- .tap_coreio1__oe(tap_coreio1__oe),
- .tap_fsm_capture(_fsm_tap_fsm_capture),
- .tap_fsm_shift(_fsm_tap_fsm_shift),
- .tap_fsm_update(_fsm_tap_fsm_update),
- .tap_io_tdo(_ioblock_tap_io_tdo),
- .tap_padio0__i(tap_padio0__i),
- .tap_padio1__i(tap_padio1__i)
- );
- _irblock _irblock (
- .ir(_irblock_ir),
- .jtag_clk(_fsm_jtag_clk),
- .jtag_rst(_fsm_jtag_rst),
- .tap_bus__tdi(tap_bus__tdi),
- .tap_fsm_capture(_fsm_tap_fsm_capture),
- .tap_fsm_isir(_fsm_tap_fsm_isir),
- .tap_fsm_shift(_fsm_tap_fsm_shift),
- .tap_fsm_update(_fsm_tap_fsm_update),
- .tdo(_irblock_tdo)
- );
- always @* begin
- tap_tdo = 1'h0;
- (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:398" *)
- casez ({ \$15 , \$3 , _fsm_tap_fsm_isir })
- /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:398" */
- 3'b??1:
- tap_tdo = _irblock_tdo;
- /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:400" */
- 3'b?1?:
- tap_tdo = _idblock_tap_id_tdo;
- /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:402" */
- 3'b1??:
- tap_tdo = _ioblock_tap_io_tdo;
- endcase
- end
- assign tap_bus__tdo = tap_tdo;
-endmodule
projects / c4m-jtag.git / commitdiff