From: Staf Verhaegen <staf@stafverhaegen.be>
Date: Sun, 15 Dec 2019 13:52:36 +0000 (+0100)
Subject: Move idcode.vhdl to test/ghdl/idcode
X-Git-Tag: 24jan2021ls180~27
X-Git-Url: https://git.libre-soc.org/?p=c4m-jtag.git;a=commitdiff_plain;h=09341bedae2f6ffc9ca1682435df2908f44d5039;hp=0022c71cf20007c831ac8c0c876e3772fef78feb

Move idcode.vhdl to test/ghdl/idcode
---

diff --git a/test/ghdl/idcode/bench_idcode.sh b/test/ghdl/idcode/bench_idcode.sh
index 6462c41..253efed 100755
--- a/test/ghdl/idcode/bench_idcode.sh
+++ b/test/ghdl/idcode/bench_idcode.sh
@@ -1,6 +1,5 @@
 #!/bin/sh
 vhdldir=`realpath ../../../c4m/vhdl/jtag`
-testvhdldir=`realpath ../../rtl/vhdl`
 opts=--std=08
 ghdl -a $opts $vhdldir/c4m_jtag_pkg.vhdl
 ghdl -a $opts $vhdldir/c4m_jtag_tap_fsm.vhdl
@@ -9,5 +8,5 @@ ghdl -a $opts $vhdldir/c4m_jtag_idblock.vhdl
 ghdl -a $opts $vhdldir/c4m_jtag_iocell.vhdl
 ghdl -a $opts $vhdldir/c4m_jtag_ioblock.vhdl
 ghdl -a $opts $vhdldir/c4m_jtag_tap_controller.vhdl
-ghdl -a $opts $testvhdldir/idcode.vhdl
+ghdl -a $opts ./idcode.vhdl
 ghdl -r $opts bench_idcode --wave=bench_idcode.ghw
diff --git a/test/ghdl/idcode/idcode.vhdl b/test/ghdl/idcode/idcode.vhdl
new file mode 100644
index 0000000..cc7d167
--- /dev/null
+++ b/test/ghdl/idcode/idcode.vhdl
@@ -0,0 +1,102 @@
+-- reset JTAG interface and then IDCODE should be shifted out
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+
+use work.c4m_jtag.ALL;
+
+entity bench_idcode is
+end bench_idcode;
+
+architecture rtl of bench_idcode is
+  signal TCK:   std_logic;
+  signal TMS:   std_logic;
+  signal TDI:   std_logic;
+  signal TDO:   std_logic;
+  signal TRST_N: std_logic;
+
+  constant CLK_PERIOD:  time := 10 ns;
+
+  procedure ClkCycle(
+    signal CLK: out std_logic;
+    CLK_PERIOD: time
+  ) is
+  begin
+    CLK <= '0';
+    wait for CLK_PERIOD/4;
+    CLK <= '1';
+    wait for CLK_PERIOD/2;
+    CLK <= '0';
+    wait for CLK_PERIOD/4;
+  end ClkCycle;
+
+  procedure ClkCycles(
+    N:  integer;
+    signal CLK: out std_logic;
+    CLK_PERIOD: time
+  ) is
+  begin
+    for i in 1 to N loop
+      ClkCycle(CLK, CLK_PERIOD);
+    end loop;
+  end ClkCycles;
+begin
+  JTAG_BLOCK: c4m_jtag_tap_controller
+    -- Use default values
+    port map (
+      TCK => TCK,
+      TMS => TMS,
+      TDI => TDI,
+      TDO => TDO,
+      TRST_N => TRST_N,
+      RESET => open,
+      CAPTURE => open,
+      SHIFT => open,
+      UPDATE => open,
+      IR => open,
+      CORE_OUT => "0",
+      CORE_IN => open,
+      CORE_EN => "0",
+      PAD_OUT => open,
+      PAD_IN => "0",
+      PAD_EN => open
+    );
+
+  SIM: process
+  begin
+    -- Reset
+    TCK <= '0';
+    TMS <= '1';
+    TDI <= '0';
+    TRST_N <= '0';
+    wait for 10*CLK_PERIOD;
+
+    TRST_N <= '1';
+    wait for CLK_PERIOD;
+
+    -- Enter RunTestIdle
+    TMS <= '0';
+    ClkCycle(TCK, CLK_PERIOD);
+    -- Enter SelectDRScan
+    TMS <= '1';
+    ClkCycle(TCK, CLK_PERIOD);
+    -- Enter Capture
+    TMS <= '0';
+    ClkCycle(TCK, CLK_PERIOD);
+    -- Enter Shift, run for 35 CLK cycles
+    TMS <= '0';
+    ClkCycles(35, TCK, CLK_PERIOD);
+    -- Enter Exit1
+    TMS <= '1';
+    ClkCycle(TCK, CLK_PERIOD);
+    -- Enter Update
+    TMS <= '1';
+    ClkCycle(TCK, CLK_PERIOD);
+    -- To TestLogicReset
+    TMS <= '1';
+    ClkCycles(4, TCK, CLK_PERIOD);
+
+    -- end simulation
+    wait;
+  end process;
+end rtl;
diff --git a/test/rtl/vhdl/idcode.vhdl b/test/rtl/vhdl/idcode.vhdl
deleted file mode 100644
index cc7d167..0000000
--- a/test/rtl/vhdl/idcode.vhdl
+++ /dev/null
@@ -1,102 +0,0 @@
--- reset JTAG interface and then IDCODE should be shifted out
-
-library ieee;
-use ieee.std_logic_1164.ALL;
-
-use work.c4m_jtag.ALL;
-
-entity bench_idcode is
-end bench_idcode;
-
-architecture rtl of bench_idcode is
-  signal TCK:   std_logic;
-  signal TMS:   std_logic;
-  signal TDI:   std_logic;
-  signal TDO:   std_logic;
-  signal TRST_N: std_logic;
-
-  constant CLK_PERIOD:  time := 10 ns;
-
-  procedure ClkCycle(
-    signal CLK: out std_logic;
-    CLK_PERIOD: time
-  ) is
-  begin
-    CLK <= '0';
-    wait for CLK_PERIOD/4;
-    CLK <= '1';
-    wait for CLK_PERIOD/2;
-    CLK <= '0';
-    wait for CLK_PERIOD/4;
-  end ClkCycle;
-
-  procedure ClkCycles(
-    N:  integer;
-    signal CLK: out std_logic;
-    CLK_PERIOD: time
-  ) is
-  begin
-    for i in 1 to N loop
-      ClkCycle(CLK, CLK_PERIOD);
-    end loop;
-  end ClkCycles;
-begin
-  JTAG_BLOCK: c4m_jtag_tap_controller
-    -- Use default values
-    port map (
-      TCK => TCK,
-      TMS => TMS,
-      TDI => TDI,
-      TDO => TDO,
-      TRST_N => TRST_N,
-      RESET => open,
-      CAPTURE => open,
-      SHIFT => open,
-      UPDATE => open,
-      IR => open,
-      CORE_OUT => "0",
-      CORE_IN => open,
-      CORE_EN => "0",
-      PAD_OUT => open,
-      PAD_IN => "0",
-      PAD_EN => open
-    );
-
-  SIM: process
-  begin
-    -- Reset
-    TCK <= '0';
-    TMS <= '1';
-    TDI <= '0';
-    TRST_N <= '0';
-    wait for 10*CLK_PERIOD;
-
-    TRST_N <= '1';
-    wait for CLK_PERIOD;
-
-    -- Enter RunTestIdle
-    TMS <= '0';
-    ClkCycle(TCK, CLK_PERIOD);
-    -- Enter SelectDRScan
-    TMS <= '1';
-    ClkCycle(TCK, CLK_PERIOD);
-    -- Enter Capture
-    TMS <= '0';
-    ClkCycle(TCK, CLK_PERIOD);
-    -- Enter Shift, run for 35 CLK cycles
-    TMS <= '0';
-    ClkCycles(35, TCK, CLK_PERIOD);
-    -- Enter Exit1
-    TMS <= '1';
-    ClkCycle(TCK, CLK_PERIOD);
-    -- Enter Update
-    TMS <= '1';
-    ClkCycle(TCK, CLK_PERIOD);
-    -- To TestLogicReset
-    TMS <= '1';
-    ClkCycles(4, TCK, CLK_PERIOD);
-
-    -- end simulation
-    wait;
-  end process;
-end rtl;