From: Staf Verhaegen <staf@stafverhaegen.be>
Date: Thu, 5 Dec 2019 16:22:20 +0000 (+0100)
Subject: Move pmod resource to own file and convert it in one function.
X-Git-Tag: 24jan2021ls180~44
X-Git-Url: https://git.libre-soc.org/?p=c4m-jtag.git;a=commitdiff_plain;h=62a29aa5ee3116835b8795ffe9ec41e9d7683e21

Move pmod resource to own file and convert it in one function.
---

diff --git a/c4m/nmigen/jtag/__init__.py b/c4m/nmigen/jtag/__init__.py
index e69de29..bfa7957 100644
--- a/c4m/nmigen/jtag/__init__.py
+++ b/c4m/nmigen/jtag/__init__.py
@@ -0,0 +1 @@
+from .pmod import *
diff --git a/c4m/nmigen/jtag/jtag.py b/c4m/nmigen/jtag/jtag.py
index 88d1292..0e4de64 100755
--- a/c4m/nmigen/jtag/jtag.py
+++ b/c4m/nmigen/jtag/jtag.py
@@ -8,53 +8,11 @@ from nmigen.lib.io import *
 from wishbone import Wishbone
 
 __all__ = [
-    "PmodJTAGMasterResource",
-    "PmodJTAGMasterAResource",
-    "PmodJTAGSlaveResource",
-    "PmodJTAGSlaveAResource",
     "JTAG",
 ]
 
 #TODO: Provide more documentation
 
-def PmodJTAGMasterResource(name, number, *, pmod, attrs=Attrs(IOSTANDARD="LVCMOS33")):
-    return Resource(name, number,
-        Subsignal("TCK", Pins("1", dir="o", conn=("pmod", pmod))),
-        Subsignal("TMS", Pins("2", dir="o", conn=("pmod", pmod))),
-        Subsignal("TDO", Pins("3", dir="o", conn=("pmod", pmod))),
-        Subsignal("TDI", Pins("4", dir="i", conn=("pmod", pmod))),
-        attrs,
-    )
-
-def PmodJTAGMasterAResource(name, number, *, pmod, attrs=Attrs(IOSTANDARD="LVCMOS33")):
-    return Resource(name, number,
-        Subsignal("TCK", Pins("1", dir="o", conn=("pmod", pmod))),
-        Subsignal("TMS", Pins("2", dir="o", conn=("pmod", pmod))),
-        Subsignal("TDO", Pins("3", dir="o", conn=("pmod", pmod))),
-        Subsignal("TDI", Pins("4", dir="i", conn=("pmod", pmod))),
-        Subsignal("TRST", PinsN("7", dir="o", conn=("pmod", pmod))),
-        attrs,
-    )
-
-def PmodJTAGSlaveResource(name, number, *, pmod, attrs=Attrs(IOSTANDARD="LVCMOS33")):
-    return Resource(name, number,
-        Subsignal("TCK", Pins("1", dir="i", conn=("pmod", pmod))),
-        Subsignal("TMS", Pins("2", dir="i", conn=("pmod", pmod))),
-        Subsignal("TDI", Pins("3", dir="i", conn=("pmod", pmod))),
-        Subsignal("TDO", Pins("4", dir="o", conn=("pmod", pmod))),
-        attrs,
-    )
-
-def PmodJTAGSlaveAResource(name, number, *, pmod, attrs=Attrs(IOSTANDARD="LVCMOS33")):
-    return Resource(name, number,
-        Subsignal("TCK", Pins("1", dir="i", conn=("pmod", pmod))),
-        Subsignal("TMS", Pins("2", dir="i", conn=("pmod", pmod))),
-        Subsignal("TDI", Pins("3", dir="i", conn=("pmod", pmod))),
-        Subsignal("TDO", Pins("4", dir="o", conn=("pmod", pmod))),
-        Subsignal("TRST", PinsN("7", dir="i", conn=("pmod", pmod))),
-        attrs,
-    )
-
 
 class ShiftReg(Elaboratable):
     def __init__(self, ircodes, length, domain):
diff --git a/c4m/nmigen/jtag/pmod.py b/c4m/nmigen/jtag/pmod.py
new file mode 100644
index 0000000..bda2f26
--- /dev/null
+++ b/c4m/nmigen/jtag/pmod.py
@@ -0,0 +1,46 @@
+from nmigen.build import *
+
+__all__ = [
+    "PmodJTAGResource",
+]
+
+
+def PmodJTAGResource(*args, pmod_name="pmod", pmod_number, attrs=None,
+                     master=False, reset=False):
+    """Get a resource for a JTAG pins on a pmod.
+
+    The pins are configured in such a way that the master pmod jtag can
+    be connected to the tap pmod with a straight cable.
+
+    Args:
+        *args: either number or name, number.
+        pmod_name (str): name of the pmod connector; default = "pmod"
+        pmod_number (int): number of pmod connector
+        attrs (Attrs): attributes for the ``Resource``
+        master (bool): wether if this a master interface
+        reset (bool): wether to include a reset signal
+    """
+    if master:
+        mosi = "o"
+        miso = "i"
+        tdo_pin = "3"
+        tdi_pin = "4"
+    else:
+        mosi = "i"
+        miso = "o"
+        tdo_pin = "4"
+        tdi_pin = "3"
+    conn = (pmod_name, pmod_number)
+
+    ios = [
+        Subsignal("tck", Pins("1", dir=mosi, conn=conn)),
+        Subsignal("tms", Pins("2", dir=mosi, conn=conn)),
+        Subsignal("tdo", Pins(tdo_pin, dir="o", conn=conn)),
+        Subsignal("tdi", Pins(tdi_pin, dir="i", conn=conn)),
+    ]
+    if reset:
+        ios.append(Subsignal("trst", PinsN("7", dir=mosi, conn=conn)))
+    if attrs is not None:
+        ios.append(attrs)
+
+    return Resource.family(*args, default_name="jtag", ios=ios)