From: Staf Verhaegen Date: Sun, 15 Dec 2019 12:54:18 +0000 (+0100) Subject: Basic nmigen generator bench for TAP top cell. X-Git-Tag: 24jan2021ls180~24 X-Git-Url: https://git.libre-soc.org/?p=c4m-jtag.git;a=commitdiff_plain;h=be7690de9e0249de63bfca484398fda075e7f5d0;ds=sidebyside Basic nmigen generator bench for TAP top cell. Simple generation with nmigen and yosys as only dependency. --- diff --git a/test/nmigen/gen/controller/Makefile b/test/nmigen/gen/controller/Makefile new file mode 100644 index 0000000..dd4ceeb --- /dev/null +++ b/test/nmigen/gen/controller/Makefile @@ -0,0 +1,27 @@ +CURDIR = $(realpath .) +TOPDIR = $(realpath ../../../..) + +NMIGENDIR := $(TOPDIR)/c4m/nmigen/jtag + +ifeq ($(PYTHONPATH),) + PYTHONPATH := $(TOPDIR) +else + PYTHONPATH := $(TOPDIR):$(PYTHONPATH) +endif +export PYTHONPATH + +OUTPUTS := top.v +INPUTS := $(addprefix $(NMIGENDIR)/,bus.py tap.py) +SCRIPT := ./generate.py + +.PHONY: all +all: $(OUTPUTS) + +# We just test if top verilog file can be generated +top.v: $(SCRIPT) $(INPUTS) + @echo "Regenerating" + @$(SCRIPT) + +.PHONY: clean +clean: + @rm -f $(OUTPUTS) diff --git a/test/nmigen/gen/controller/generate.py b/test/nmigen/gen/controller/generate.py new file mode 100755 index 0000000..de8d6a9 --- /dev/null +++ b/test/nmigen/gen/controller/generate.py @@ -0,0 +1,20 @@ +#!/bin/env python3 +from nmigen import * +from nmigen.back.verilog import convert +from nmigen.build import Platform + +from c4m.nmigen.jtag import TAP + +class DummyPlatform(Platform): + resources = [] + connectors = [] + required_tools = ["yosys"] + + def toolchain_prepare(self, fragment, name, **kwargs): + raise NotImplementedError + +tap = TAP(2) +f = open("top.v", "w") +f.write(convert(tap, platform=DummyPlatform())) +f.close() + diff --git a/test/nmigen/gen/controller/top.v b/test/nmigen/gen/controller/top.v new file mode 100644 index 0000000..91f7871 --- /dev/null +++ b/test/nmigen/gen/controller/top.v @@ -0,0 +1,382 @@ +/* Generated by Yosys 0.9+932 (git sha1 ff8529a, gcc 4.8.5 -fPIC -Os) */ + +(* generator = "nMigen" *) +(* \nmigen.hierarchy = "top._fsm" *) +module _fsm(tap_fsm_isdr, jtag_clk, tap_bus__tck, tap_bus__tms, tap_fsm_capture, tap_fsm_shift, tap_fsm_update, jtag_rst, tap_fsm_isir); + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:359" *) + output jtag_clk; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:359" *) + output jtag_rst; + (* src = "./generate.py:16" *) + input tap_bus__tck; + (* src = "./generate.py:16" *) + input tap_bus__tms; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:25" *) + output tap_fsm_capture; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:24" *) + output tap_fsm_isdr; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:23" *) + output tap_fsm_isir; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:26" *) + output tap_fsm_shift; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:27" *) + output tap_fsm_update; + c4m_jtag_tap_fsm inst ( + .capture(tap_fsm_capture), + .isdr(tap_fsm_isdr), + .isir(tap_fsm_isir), + .reset(jtag_rst), + .shift(tap_fsm_shift), + .tck(tap_bus__tck), + .tms(tap_bus__tms), + .trst_n(1'h1), + .update(tap_fsm_update) + ); + assign jtag_clk = tap_bus__tck; +endmodule + +(* generator = "nMigen" *) +(* \nmigen.hierarchy = "top._idblock" *) +module _idblock(ir, tap_id_tdo, jtag_clk, tap_fsm_capture, tap_fsm_shift, tap_bus__tdi, jtag_rst, tap_fsm_isdr); + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *) + wire \$1 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:380" *) + wire \$11 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:114" *) + wire [31:0] \$13 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *) + wire \$3 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:379" *) + wire \$5 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *) + wire \$7 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *) + wire \$9 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:60" *) + input [1:0] ir; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:359" *) + input jtag_clk; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:359" *) + input jtag_rst; + (* src = "./generate.py:16" *) + input tap_bus__tdi; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:25" *) + input tap_fsm_capture; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:24" *) + input tap_fsm_isdr; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:26" *) + input tap_fsm_shift; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:107" *) + reg [31:0] tap_id_sr = 32'd0; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:107" *) + reg [31:0] \tap_id_sr$next ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:97" *) + output tap_id_tdo; + assign \$9 = tap_fsm_isdr & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *) \$7 ; + assign \$11 = \$9 & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:380" *) tap_fsm_shift; + assign \$13 = + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:114" *) { tap_bus__tdi, tap_id_sr[31:2] }; + assign \$1 = ir == (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *) 1'h1; + assign \$3 = tap_fsm_isdr & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *) \$1 ; + assign \$5 = \$3 & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:379" *) tap_fsm_capture; + assign \$7 = ir == (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *) 1'h1; + always @(posedge jtag_clk) + tap_id_sr <= \tap_id_sr$next ; + always @* begin + \tap_id_sr$next = tap_id_sr; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:111" *) + casez ({ \$11 , \$5 }) + /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:111" */ + 2'b?1: + \tap_id_sr$next = 32'd6399; + /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:113" */ + 2'b1?: + \tap_id_sr$next = \$13 ; + endcase + end + assign tap_id_tdo = tap_id_sr[0]; +endmodule + +(* generator = "nMigen" *) +(* \nmigen.hierarchy = "top._ioblock" *) +module _ioblock(tap_io_tdo, tap_fsm_capture, tap_fsm_shift, tap_fsm_update, tap_bus__tdi, clk, tap_coreio0__o, tap_coreio1__o, tap_coreio0__oe, tap_coreio1__oe, tap_padio0__i, tap_padio1__i, ir); + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ir.py:538" *) + input clk; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:60" *) + input [1:0] ir; + (* src = "./generate.py:16" *) + input tap_bus__tdi; + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *) + wire tap_coreio0__i; + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *) + input tap_coreio0__o; + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *) + input tap_coreio0__oe; + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *) + wire tap_coreio1__i; + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *) + input tap_coreio1__o; + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *) + input tap_coreio1__oe; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:25" *) + input tap_fsm_capture; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:26" *) + input tap_fsm_shift; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:27" *) + input tap_fsm_update; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:194" *) + output tap_io_tdo; + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *) + input tap_padio0__i; + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *) + wire tap_padio0__o; + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *) + wire tap_padio0__oe; + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *) + input tap_padio1__i; + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *) + wire tap_padio1__o; + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *) + wire tap_padio1__oe; + jtag_ioblock_2_2 inst ( + .capture(tap_fsm_capture), + .core_en({ tap_coreio1__oe, tap_coreio0__oe }), + .core_in({ tap_coreio1__i, tap_coreio0__i }), + .core_out({ tap_coreio1__o, tap_coreio0__o }), + .ir(ir), + .pad_en({ tap_padio1__oe, tap_padio0__oe }), + .pad_in({ tap_padio1__i, tap_padio0__i }), + .pad_out({ tap_padio1__o, tap_padio0__o }), + .shift(tap_fsm_shift), + .tck(clk), + .tdi(tap_bus__tdi), + .tdo(tap_io_tdo), + .update(tap_fsm_update) + ); +endmodule + +(* generator = "nMigen" *) +(* \nmigen.hierarchy = "top._irblock" *) +module _irblock(ir, tdo, jtag_clk, tap_fsm_capture, tap_fsm_shift, tap_fsm_update, tap_bus__tdi, jtag_rst, tap_fsm_isir); + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:368" *) + wire \$1 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:369" *) + wire \$11 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:370" *) + wire \$13 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:369" *) + wire \$3 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:370" *) + wire \$5 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:77" *) + wire [1:0] \$7 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:368" *) + wire \$9 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:60" *) + output [1:0] ir; + reg [1:0] ir = 2'h1; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:60" *) + reg [1:0] \ir$next ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:359" *) + input jtag_clk; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:359" *) + input jtag_rst; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:71" *) + reg [1:0] shift_ir = 2'h0; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:71" *) + reg [1:0] \shift_ir$next ; + (* src = "./generate.py:16" *) + input tap_bus__tdi; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:25" *) + input tap_fsm_capture; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:23" *) + input tap_fsm_isir; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:26" *) + input tap_fsm_shift; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:27" *) + input tap_fsm_update; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:61" *) + output tdo; + assign \$9 = tap_fsm_isir & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:368" *) tap_fsm_capture; + assign \$11 = tap_fsm_isir & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:369" *) tap_fsm_shift; + assign \$13 = tap_fsm_isir & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:370" *) tap_fsm_update; + assign \$1 = tap_fsm_isir & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:368" *) tap_fsm_capture; + assign \$3 = tap_fsm_isir & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:369" *) tap_fsm_shift; + assign \$5 = tap_fsm_isir & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:370" *) tap_fsm_update; + assign \$7 = + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:77" *) tap_bus__tdi; + always @(posedge jtag_clk) + ir <= \ir$next ; + always @(posedge jtag_clk) + shift_ir <= \shift_ir$next ; + always @* begin + \shift_ir$next = shift_ir; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:74" *) + casez ({ \$5 , \$3 , \$1 }) + /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:74" */ + 3'b??1: + \shift_ir$next = ir; + /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:76" */ + 3'b?1?: + \shift_ir$next = \$7 ; + endcase + end + always @* begin + \ir$next = ir; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:74" *) + casez ({ \$13 , \$11 , \$9 }) + /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:74" */ + 3'b??1: + /* empty */; + /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:76" */ + 3'b?1?: + /* empty */; + /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:78" */ + 3'b1??: + \ir$next = shift_ir; + endcase + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/xfrm.py:528" *) + casez (jtag_rst) + 1'h1: + \ir$next = 2'h1; + endcase + end + assign tdo = ir[0]; +endmodule + +(* generator = "nMigen" *) +(* top = 1 *) +(* \nmigen.hierarchy = "top" *) +module top(tap_bus__tms, tap_bus__tdi, clk, tap_coreio0__o, tap_coreio1__o, tap_coreio0__oe, tap_coreio1__oe, tap_padio0__i, tap_padio1__i, tap_bus__tck); + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *) + wire \$1 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *) + wire \$11 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *) + wire \$13 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *) + wire \$15 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *) + wire \$3 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *) + wire \$5 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *) + wire \$7 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *) + wire \$9 ; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:359" *) + wire _fsm_jtag_clk; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:359" *) + wire _fsm_jtag_rst; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:25" *) + wire _fsm_tap_fsm_capture; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:24" *) + wire _fsm_tap_fsm_isdr; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:23" *) + wire _fsm_tap_fsm_isir; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:26" *) + wire _fsm_tap_fsm_shift; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:27" *) + wire _fsm_tap_fsm_update; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:97" *) + wire _idblock_tap_id_tdo; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:194" *) + wire _ioblock_tap_io_tdo; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:60" *) + wire [1:0] _irblock_ir; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:61" *) + wire _irblock_tdo; + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ir.py:538" *) + input clk; + (* src = "./generate.py:16" *) + input tap_bus__tck; + (* src = "./generate.py:16" *) + input tap_bus__tdi; + (* src = "./generate.py:16" *) + wire tap_bus__tdo; + (* src = "./generate.py:16" *) + input tap_bus__tms; + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *) + input tap_coreio0__o; + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *) + input tap_coreio0__oe; + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *) + input tap_coreio1__o; + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *) + input tap_coreio1__oe; + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *) + input tap_padio0__i; + (* src = "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/ast.py:1075" *) + input tap_padio1__i; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:397" *) + reg tap_tdo; + assign \$9 = \$5 | (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *) \$7 ; + assign \$11 = _irblock_ir == (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *) 2'h2; + assign \$13 = \$9 | (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *) \$11 ; + assign \$15 = _fsm_tap_fsm_isdr & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *) \$13 ; + assign \$1 = _irblock_ir == (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *) 1'h1; + assign \$3 = _fsm_tap_fsm_isdr & (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:375" *) \$1 ; + assign \$5 = _irblock_ir == (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *) 1'h0; + assign \$7 = _irblock_ir == (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:388" *) 2'h2; + _fsm _fsm ( + .jtag_clk(_fsm_jtag_clk), + .jtag_rst(_fsm_jtag_rst), + .tap_bus__tck(tap_bus__tck), + .tap_bus__tms(tap_bus__tms), + .tap_fsm_capture(_fsm_tap_fsm_capture), + .tap_fsm_isdr(_fsm_tap_fsm_isdr), + .tap_fsm_isir(_fsm_tap_fsm_isir), + .tap_fsm_shift(_fsm_tap_fsm_shift), + .tap_fsm_update(_fsm_tap_fsm_update) + ); + _idblock _idblock ( + .ir(_irblock_ir), + .jtag_clk(_fsm_jtag_clk), + .jtag_rst(_fsm_jtag_rst), + .tap_bus__tdi(tap_bus__tdi), + .tap_fsm_capture(_fsm_tap_fsm_capture), + .tap_fsm_isdr(_fsm_tap_fsm_isdr), + .tap_fsm_shift(_fsm_tap_fsm_shift), + .tap_id_tdo(_idblock_tap_id_tdo) + ); + _ioblock _ioblock ( + .clk(clk), + .ir(_irblock_ir), + .tap_bus__tdi(tap_bus__tdi), + .tap_coreio0__o(tap_coreio0__o), + .tap_coreio0__oe(tap_coreio0__oe), + .tap_coreio1__o(tap_coreio1__o), + .tap_coreio1__oe(tap_coreio1__oe), + .tap_fsm_capture(_fsm_tap_fsm_capture), + .tap_fsm_shift(_fsm_tap_fsm_shift), + .tap_fsm_update(_fsm_tap_fsm_update), + .tap_io_tdo(_ioblock_tap_io_tdo), + .tap_padio0__i(tap_padio0__i), + .tap_padio1__i(tap_padio1__i) + ); + _irblock _irblock ( + .ir(_irblock_ir), + .jtag_clk(_fsm_jtag_clk), + .jtag_rst(_fsm_jtag_rst), + .tap_bus__tdi(tap_bus__tdi), + .tap_fsm_capture(_fsm_tap_fsm_capture), + .tap_fsm_isir(_fsm_tap_fsm_isir), + .tap_fsm_shift(_fsm_tap_fsm_shift), + .tap_fsm_update(_fsm_tap_fsm_update), + .tdo(_irblock_tdo) + ); + always @* begin + tap_tdo = 1'h0; + (* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:398" *) + casez ({ \$15 , \$3 , _fsm_tap_fsm_isir }) + /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:398" */ + 3'b??1: + tap_tdo = _irblock_tdo; + /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:400" */ + 3'b?1?: + tap_tdo = _idblock_tap_id_tdo; + /* src = "/home/verhaegs/eda/code/c4m_jtag/c4m/nmigen/jtag/tap.py:402" */ + 3'b1??: + tap_tdo = _ioblock_tap_io_tdo; + endcase + end + assign tap_bus__tdo = tap_tdo; +endmodule