Merge branch 'upstream_libresoc' into libresoc_master
[c4m-jtag.git] / test /
2021-04-22 Staf VerhaegenDouble empty lines between top level definitions.
2021-04-22 Staf VerhaegenDouble empty lines between top level definitions.
2021-04-21 Staf VerhaegenRemove generated test file.
2021-04-21 Staf VerhaegenFix path for env
2021-04-21 Staf VerhaegenRemove generated test file.
2021-04-21 Staf VerhaegenFix path for env
2020-01-06 Staf VerhaegenUpdate the unit tests.
2020-01-06 Staf VerhaegenMade nmigen code independent of VHDL code.
2020-01-06 Staf VerhaegenSupport for different IO types in VHDL code.
2019-12-17 Staf VerhaegenAlso clean python cache.
2019-12-16 Staf VerhaegenAdded test bench for nmigen TAP with cocotb.
2019-12-16 Staf VerhaegenBasic nmigen generator bench for TAP top cell.
2019-12-16 Staf VerhaegenFix paths after move.
2019-12-16 Staf Verhaegen[broken]Moved test benches to test/vhdl
2019-12-16 Staf VerhaegenMove idcode.vhdl to test/ghdl/idcode
2019-12-16 Staf VerhaegenRemove unused bench
2019-12-14 Staf VerhaegenMade STATE and NEXT_STATE internal to c4m_jtag_tap_fsm.
2019-12-06 Staf VerhaegenFix code after move
2019-12-06 Staf Verhaegen[broken]Move code