c4m-jtag.git
16 months agoUpdate the unit tests.
Staf Verhaegen [Tue, 17 Dec 2019 19:26:08 +0000 (20:26 +0100)]
Update the unit tests.

* Add test for custom shiftreg
* Add Wishbone JTAG port test.

16 months agococotb improvements
Staf Verhaegen [Tue, 17 Dec 2019 16:53:08 +0000 (17:53 +0100)]
cocotb improvements

* Made ir_width configurable.
* Allow to use BinaryValue for load_ir.

16 months agoMade nmigen code independent of VHDL code.
Staf Verhaegen [Mon, 6 Jan 2020 17:06:05 +0000 (18:06 +0100)]
Made nmigen code independent of VHDL code.

All blocks have been converted to nmigen.

16 months agoSupport for different IO types in VHDL code.
Staf Verhaegen [Mon, 6 Jan 2020 17:05:06 +0000 (18:05 +0100)]
Support for different IO types in VHDL code.

IO cells can now be input, output, tri-state output, tri-state
inout. Update tests and added separate test for c4m_jtag_ioblock.

16 months agoForce passing by name for TAP.add_shiftreg().
Staf Verhaegen [Tue, 17 Dec 2019 19:26:46 +0000 (20:26 +0100)]
Force passing by name for TAP.add_shiftreg().

16 months agoAlso clean python cache.
Staf Verhaegen [Tue, 17 Dec 2019 19:27:08 +0000 (20:27 +0100)]
Also clean python cache.

16 months agoAdded test bench for nmigen TAP with cocotb.
Staf Verhaegen [Mon, 16 Dec 2019 10:00:04 +0000 (11:00 +0100)]
Added test bench for nmigen TAP with cocotb.

Based on vhdl controller test bench.

16 months agoFix order of iocells in ioblock.
Staf Verhaegen [Mon, 16 Dec 2019 15:36:45 +0000 (16:36 +0100)]
Fix order of iocells in ioblock.

16 months agoSpecify names for TAP signals.
Staf Verhaegen [Mon, 16 Dec 2019 09:45:15 +0000 (10:45 +0100)]
Specify names for TAP signals.

16 months agoBasic nmigen generator bench for TAP top cell.
Staf Verhaegen [Sun, 15 Dec 2019 12:54:18 +0000 (13:54 +0100)]
Basic nmigen generator bench for TAP top cell.

Simple generation with nmigen and yosys as only dependency.

16 months agoFix paths after move.
Staf Verhaegen [Sun, 15 Dec 2019 14:19:51 +0000 (15:19 +0100)]
Fix paths after move.

16 months ago[broken]Moved test benches to test/vhdl
Staf Verhaegen [Sun, 15 Dec 2019 13:55:36 +0000 (14:55 +0100)]
[broken]Moved test benches to test/vhdl

test/vhdl will be for test benches of the vhdl code; test/nmigen for the
nmigen code.
This just moves the files. They will be fixed in next commit.

16 months agoMove idcode.vhdl to test/ghdl/idcode
Staf Verhaegen [Sun, 15 Dec 2019 13:52:36 +0000 (14:52 +0100)]
Move idcode.vhdl to test/ghdl/idcode

16 months agoRemove unused bench
Staf Verhaegen [Sun, 15 Dec 2019 13:49:46 +0000 (14:49 +0100)]
Remove unused bench

16 months agoMade STATE and NEXT_STATE internal to c4m_jtag_tap_fsm.
Staf Verhaegen [Tue, 10 Dec 2019 20:31:16 +0000 (21:31 +0100)]
Made STATE and NEXT_STATE internal to c4m_jtag_tap_fsm.

This also makes the STATE_TYPE type internal to c4m_jtag_tap_fsm.

16 months agoPass VERSION generic from controller to idblock.
Staf Verhaegen [Tue, 10 Dec 2019 20:17:18 +0000 (21:17 +0100)]
Pass VERSION generic from controller to idblock.

16 months agoMoved function definitions before component definitions in pkg.
Staf Verhaegen [Tue, 10 Dec 2019 20:16:00 +0000 (21:16 +0100)]
Moved function definitions before component definitions in pkg.

16 months agoAdded TODO for IOMODEs.
Staf Verhaegen [Tue, 10 Dec 2019 20:14:31 +0000 (21:14 +0100)]
Added TODO for IOMODEs.

16 months agoAdd top controller instance from nmigen code.
Staf Verhaegen [Sun, 8 Dec 2019 09:48:56 +0000 (10:48 +0100)]
Add top controller instance from nmigen code.

Currently ghdlsynth needs instantiated cell with given generic values.

17 months agoSimplify signal generation for TAP wishbone interfaces.
Staf Verhaegen [Fri, 6 Dec 2019 19:06:49 +0000 (20:06 +0100)]
Simplify signal generation for TAP wishbone interfaces.

17 months agoUse Elif for third m.next assignment.
Staf Verhaegen [Fri, 6 Dec 2019 19:06:06 +0000 (20:06 +0100)]
Use Elif for third m.next assignment.

This way m.next assignments are done in one If/Elif statements for
the "IDLE" state and not in two different If statements.

17 months agoUse Wishbone code from nmigen-soc.
Staf Verhaegen [Fri, 6 Dec 2019 10:40:40 +0000 (11:40 +0100)]
Use Wishbone code from nmigen-soc.

17 months agoSupport JTAG bus with a reset signal.
Staf Verhaegen [Fri, 6 Dec 2019 11:07:27 +0000 (12:07 +0100)]
Support JTAG bus with a reset signal.

17 months agoRework ShiftReg and Wishbone elaboration.
Staf Verhaegen [Fri, 6 Dec 2019 10:47:43 +0000 (11:47 +0100)]
Rework ShiftReg and Wishbone elaboration.

- ShiftReg is now a Record subclass just providing the interface for
  user code.
- JTAGWishbone class is removed.
- elaboration for ShiftReg and Wishbone is now done in
 _elaborate_shiftregs() and _elaborate_whishbones() TAP methods.

17 months agoUse the JTAG Interface class as bus.
Staf Verhaegen [Fri, 6 Dec 2019 10:17:48 +0000 (11:17 +0100)]
Use the JTAG Interface class as bus.

17 months agoGet Wishbone from c4m lib.
Staf Verhaegen [Fri, 6 Dec 2019 09:46:18 +0000 (10:46 +0100)]
Get Wishbone from c4m lib.

17 months agoRename JTAG to TAP.
Staf Verhaegen [Fri, 6 Dec 2019 09:43:10 +0000 (10:43 +0100)]
Rename JTAG to TAP.

17 months agoRenamed jtag.py -> tap.py.
Staf Verhaegen [Thu, 5 Dec 2019 19:48:18 +0000 (20:48 +0100)]
Renamed jtag.py -> tap.py.

17 months agoAdded JTAG bus interface.
Staf Verhaegen [Thu, 5 Dec 2019 19:43:26 +0000 (20:43 +0100)]
Added JTAG bus interface.

17 months agoMove pmod resource to own file and convert it in one function.
Staf Verhaegen [Thu, 5 Dec 2019 16:22:20 +0000 (17:22 +0100)]
Move pmod resource to own file and convert it in one function.

17 months agopython setuptools files
Staf Verhaegen [Wed, 4 Dec 2019 19:50:13 +0000 (20:50 +0100)]
python setuptools files

17 months agoFix code after move
Staf Verhaegen [Wed, 4 Dec 2019 16:36:22 +0000 (17:36 +0100)]
Fix code after move

* tests fixed
* path to vhdl source

17 months ago[broken]Move code
Staf Verhaegen [Fri, 6 Dec 2019 18:07:41 +0000 (19:07 +0100)]
[broken]Move code

Moved files without any changes to easily track later changes.

17 months agoSetup new structure for code
Staf Verhaegen [Wed, 4 Dec 2019 15:29:31 +0000 (16:29 +0100)]
Setup new structure for code

New structure will be compatible with easy pip/conda installing.

17 months agoMade _add_files static method of JTAG.
Staf Verhaegen [Thu, 5 Dec 2019 19:39:50 +0000 (20:39 +0100)]
Made _add_files static method of JTAG.

17 months agoUpdate test code for interface change of c4m_jtag_tap_controller.
Staf Verhaegen [Wed, 4 Dec 2019 16:34:23 +0000 (17:34 +0100)]
Update test code for interface change of c4m_jtag_tap_controller.

17 months agoHandle stall signal.
Staf Verhaegen [Fri, 6 Dec 2019 16:09:26 +0000 (17:09 +0100)]
Handle stall signal.

17 months agoAdded nmigen wrapper and support code for JTAG interface.
Staf Verhaegen [Wed, 13 Nov 2019 11:32:55 +0000 (12:32 +0100)]
Added nmigen wrapper and support code for JTAG interface.

nmigen code has support for adding shift registers and a Wishbone bus
master that is drive by JTAG commands.

18 months agoOnly add assert statement if DEBUG generic is true.
Staf Verhaegen [Tue, 29 Oct 2019 12:02:21 +0000 (13:02 +0100)]
Only add assert statement if DEBUG generic is true.

Default value is false.

19 months agococotb/c4m_jtag: support trst_n to be None.
Staf Verhaegen [Thu, 3 Oct 2019 14:47:47 +0000 (16:47 +0200)]
cocotb/c4m_jtag: support trst_n to be None.

19 months agoc4m_jtag_tap_controller: Remove TAPSTATE_TYPE signals and TDO_EN from interface
Staf Verhaegen [Thu, 3 Oct 2019 14:46:27 +0000 (16:46 +0200)]
c4m_jtag_tap_controller: Remove TAPSTATE_TYPE signals and TDO_EN from interface

20 months agoclean up unused python import statements
Staf Verhaegen [Mon, 26 Aug 2019 19:02:39 +0000 (21:02 +0200)]
clean up unused python import statements

22 months agoIDCODE:
Staf Verhaegen [Sun, 7 Jul 2019 16:29:06 +0000 (18:29 +0200)]
IDCODE:
- provide default manufacturer ID that is invalid according to spec
- provide default for all MANUFACTURER, PART_NUMBER and VERSION

2 years agoDon't use tri-state logic for TDO; introduce TDO_EN signal to indicate when TDO is...
Staf Verhaegen [Mon, 25 Jun 2018 16:48:03 +0000 (18:48 +0200)]
Don't use tri-state logic for TDO; introduce TDO_EN signal to indicate when TDO is valid.

Add assert for conflicting TDO assignment.

2 years agoSimulation setup improvements:
Staf Verhaegen [Mon, 25 Jun 2018 16:46:28 +0000 (18:46 +0200)]
Simulation setup improvements:

 * Use cocotb-path to get cocotb install dir
 * Use relative paths to find source code for simulation
 * Remove rm dual_serial test
 * Ignore build directory

3 years agoAdded SVF_Executor class that allows to execute a SVF file through a JTAG_Master...
Staf Verhaegen [Sat, 14 Apr 2018 09:28:44 +0000 (11:28 +0200)]
Added SVF_Executor class that allows to execute a SVF file through a JTAG_Master object

Currently only limited implementation only enough to run demos in simulation
on the Retro_uC.

3 years agoAdded SVF grammar parser
Staf Verhaegen [Sat, 14 Apr 2018 09:20:36 +0000 (11:20 +0200)]
Added SVF grammar parser

Using modgrammar (can be installed with pip)
TODO: PIO, PIOMAP

3 years agoJTAG_master class: fix bug that wrongly changed state to Scan when TMS is 0
Staf Verhaegen [Sat, 14 Apr 2018 09:18:56 +0000 (11:18 +0200)]
JTAG_master class: fix bug that wrongly changed state to Scan when TMS is 0

3 years agoJTAG_master class: document need for manual setting of state after using change_state...
Staf Verhaegen [Sat, 14 Apr 2018 09:17:45 +0000 (11:17 +0200)]
JTAG_master class: document need for manual setting of state after using change_state method

3 years agoFix ghdl sim script.
Staf Verhaegen [Sat, 25 Nov 2017 15:44:05 +0000 (16:44 +0100)]
Fix ghdl sim script.

3 years agoImport the JTAG interface code as used for the Chips4Maker pilot Retro-uC
Staf Verhaegen [Sun, 27 Aug 2017 20:05:24 +0000 (22:05 +0200)]
Import the JTAG interface code as used for the Chips4Maker pilot Retro-uC

This code has currently been tested in FPGA through a buspirate so should
already be functional.