From d16780cd171a61b61724572db7d2c28d1f096a2f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 16 Apr 2021 21:00:26 +0100 Subject: [PATCH] underscore names on submodules possibly interfering with verilator --- c4m/nmigen/jtag/tap.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/c4m/nmigen/jtag/tap.py b/c4m/nmigen/jtag/tap.py index dff63ac..5743363 100755 --- a/c4m/nmigen/jtag/tap.py +++ b/c4m/nmigen/jtag/tap.py @@ -355,13 +355,13 @@ class TAP(Elaboratable): cmd_preload = 2 cmd_bypass = 2**ir_width - 1 # All ones - m.submodules._fsm = fsm = _FSM(bus=self.bus) + m.submodules.fsm = fsm = _FSM(bus=self.bus) m.domains.posjtag = fsm.posjtag m.domains.negjtag = fsm.negjtag # IR block select_ir = fsm.isir - m.submodules._irblock = irblock = _IRBlock( + m.submodules.irblock = irblock = _IRBlock( ir_width=ir_width, cmd_idcode=cmd_idcode, tdi=self.bus.tdi, capture=(fsm.isir & fsm.capture), shift=(fsm.isir & fsm.shift), @@ -376,7 +376,7 @@ class TAP(Elaboratable): m.d.comb += select_id.eq(fsm.isdr & ((ir == cmd_idcode) | (ir == cmd_bypass))) m.d.comb += id_bypass.eq(ir == cmd_bypass) - m.submodules._idblock = idblock = _IDBypassBlock( + m.submodules.idblock = idblock = _IDBypassBlock( manufacturer_id=self._manufacturer_id, part_number=self._part_number, version=self._version, tdi=self.bus.tdi, -- 2.30.2