add verilog-wishbone (for async bridge) to hdl-dev-ls2

diff --git a/hdl-dev-ls2 b/hdl-dev-ls2
index 34a801a0720a69c68105b46eac269c67136b4f4f..3e582284d3202b84e9f7f071de78a15031116998 100755 (executable)
--- a/hdl-dev-ls2
+++ b/hdl-dev-ls2
@@ -14,6 +14,7 @@ git clone https://git.libre-soc.org/git/lambdasoc.git
 git clone https://git.libre-soc.org/git/microwatt.git tercel-qspi
 git clone https://github.com/freecores/uart16550
 git clone https://github.com/freecores/ethmac
+git clone https://github.com/alexforencich/verilog-wishbone
 
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 # lambdasoc