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HEAD
Remove verilog header files built from Chisel .prm file.
[freedom-sifive.git]
/
.gitmodules
1
[submodule "rocket-chip"]
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path = rocket-chip
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url = https://github.com/ucb-bar/rocket-chip.git
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[submodule "sifive-blocks"]
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path = sifive-blocks
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url = https://github.com/sifive/sifive-blocks.git