Remove verilog header files built from Chisel .prm file.
[freedom-sifive.git] / .gitmodules
1 [submodule "rocket-chip"]
2 path = rocket-chip
3 url = https://github.com/ucb-bar/rocket-chip.git
4 [submodule "sifive-blocks"]
5 path = sifive-blocks
6 url = https://github.com/sifive/sifive-blocks.git