Updates to Freedom SoCs
[freedom-sifive.git] / Makefile.e300artydevkit
1 # See LICENSE for license details.
2 base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
3 BUILD_DIR := $(base_dir)/builds/e300artydevkit
4 FPGA_DIR := $(base_dir)/fpga-shells/xilinx
5 MODEL := E300ArtyDevKitFPGAChip
6 PROJECT := sifive.freedom.everywhere.e300artydevkit
7 CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit
8 export CONFIG := E300ArtyDevKitConfig
9 export BOARD := arty
10 export BOOTROM_DIR := $(base_dir)/bootrom/xip
11
12 rocketchip_dir := $(base_dir)/rocket-chip
13 sifiveblocks_dir := $(base_dir)/sifive-blocks
14 VSRCS := \
15 $(rocketchip_dir)/vsrc/AsyncResetReg.v \
16 $(rocketchip_dir)/vsrc/plusarg_reader.v \
17 $(sifiveblocks_dir)/vsrc/SRLatch.v \
18 $(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
19 $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
20 $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
21
22 include common.mk