README.md

   1 Freedom
   2 =======
   3
   4 This repository contains the RTL created by SiFive for its Freedom E300 and U500
   5 platforms. The Freedom E310 Arty FPGA Dev Kit implements the Freedom E300
   6 Platform and is designed to be mapped onto an [Arty FPGA Evaluation
   7 Kit](https://www.xilinx.com/products/boards-and-kits/arty.html). The Freedom
   8 U500 VC707 FPGA Dev Kit implements the Freedom U500 Platform and is designed to
   9 be mapped onto a [VC707 FPGA Evaluation
  10 Kit](https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.html).
  11 Both systems boot autonomously and can be controlled via an external debugger.
  12
  13 Please read the section corresponding to the kit you are interested in for
  14 instructions on how to use this repo.
  15
  16 Software Requirement
  17 --------------------
  18
  19 To compile the bootloaders for both Freedom E300 Arty and U500 VC707
  20 FPGA dev kits, the RISC-V software toolchain must be installed locally and
  21 set the $(RISCV) environment variable to point to the location of where the
  22 RISC-V toolchains are installed. You can build the toolchain from scratch
  23 or download the tools here: https://www.sifive.com/products/tools/
  24
  25
  26 Freedom E300 Arty FPGA Dev Kit
  27 ------------------------------
  28
  29 The Freedom E300 Arty FPGA Dev Kit implements a Freedom E300 chip.
  30
  31 ### How to build
  32
  33 The Makefile corresponding to the Freedom E300 Arty FPGA Dev Kit is
  34 `Makefile.e300artydevkit` and it consists of two main targets:
  35
  36 - `verilog`: to compile the Chisel source files and generate the Verilog files.
  37 - `mcs`: to create a Configuration Memory File (.mcs) that can be programmed
  38 onto an Arty FPGA board.
  39
  40 To execute these targets, you can run the following commands:
  41
  42 ```sh
  43 $ make -f Makefile.e300artydevkit verilog
  44 $ make -f Makefile.e300artydevkit mcs
  45 ```
  46
  47 These will place the files under `builds/e300artydevkit`.
  48
  49 Note that in order to run the `mcs` target, you need to have the `vivado`
  50 executable on your `PATH`.
  51
  52 ### Bootrom
  53
  54 The default bootrom consists of a program that immediately jumps to address
  55 0x20400000, which is 0x00400000 bytes into the SPI flash memory on the Arty
  56 board.
  57
  58
  59 Freedom U500 VC707 FPGA Dev Kit
  60 -------------------------------
  61
  62 The Freedom U500 VC707 FPGA Dev Kit implements the Freedom U500 platform.
  63
  64 ### How to build
  65
  66 The Makefile corresponding to the Freedom U500 VC707 FPGA Dev Kit is
  67 `Makefile.u500vc707devkit` and it consists of two main targets:
  68
  69 - `verilog`: to compile the Chisel source files and generate the Verilog files.
  70 - `mcs`: to create a Configuration Memory File (.mcs) that can be programmed
  71 onto an VC707 FPGA board.
  72
  73 To execute these targets, you can run the following commands:
  74
  75 ```sh
  76 $ make -f Makefile.u500vc707devkit verilog
  77 $ make -f Makefile.u500vc707devkit mcs
  78 ```
  79
  80 These will place the files under `builds/u500vc707devkit`.
  81
  82 Note that in order to run the `mcs` target, you need to have the `vivado`
  83 executable on your `PATH`.
  84
  85 ### Bootrom
  86
  87 The default bootrom consists of a bootloader that loads a program off the SD
  88 card slot on the VC707 board.