README.md

   1 Freedom
   2 =======
   3
   4 This repository contains the RTL created by SiFive for its Freedom E300 and U500
   5 platforms. The Freedom E310 Arty FPGA Dev Kit implements the Freedom E300
   6 Platform and is designed to be mapped onto an [Arty FPGA Evaluation
   7 Kit](https://www.xilinx.com/products/boards-and-kits/arty.html). The Freedom
   8 U500 VC707 FPGA Dev Kit implements the Freedom U500 Platform and is designed to
   9 be mapped onto a [VC707 FPGA Evaluation
  10 Kit](https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.html).
  11
  12 Please read the section corresponding to the kit you are interested in for
  13 instructions on how to use this repo.
  14
  15
  16 Freedom E310 Arty FPGA Dev Kit
  17 ------------------------------
  18
  19 The Freedom E310 Arty FPGA Dev Kit implements a Freedom E310 chip.
  20
  21 ### How to build
  22
  23 The Makefile corresponding to the Freedom E310 Arty FPGA Dev Kit is
  24 `Makefile.e300artydevkit` and it consists of two main targets:
  25
  26 - `verilog`: to compile the Chisel source files and generate the Verilog files.
  27 - `mcs`: to create a Configuration Memory File (.mcs) that can be programmed
  28 onto an Arty FPGA board.
  29
  30 To execute these targets, you can run the following commands:
  31
  32 ```sh
  33 $ make -f Makefile.e300artydevkit verilog
  34 $ make -f Makefile.e300artydevkit mcs
  35 ```
  36
  37 These will place the files under `builds/e300artydevkit`.
  38
  39 Note that in order to run the `mcs` target, you need to have the `vivado`
  40 executable on your `PATH`.
  41
  42 ### Bootrom
  43
  44 The default bootrom consists of a program that immediately jumps to address
  45 0x20400000, which is 0x00400000 bytes into the SPI flash memory on the Arty
  46 board.
  47
  48
  49 Freedom U500 VC707 FPGA Dev Kit
  50 -------------------------------
  51
  52 The Freedom U500 VC707 FPGA Dev Kit implements the Freedom U500 platform.
  53
  54 ### How to build
  55
  56 The Makefile corresponding to the Freedom U500 VC707 FPGA Dev Kit is
  57 `Makefile.u500vc707devkit` and it consists of two main targets:
  58
  59 - `verilog`: to compile the Chisel source files and generate the Verilog files.
  60 - `mcs`: to create a Configuration Memory File (.mcs) that can be programmed
  61 onto an VC707 FPGA board.
  62
  63 To execute these targets, you can run the following commands:
  64
  65 ```sh
  66 $ make -f Makefile.u500vc707devkit verilog
  67 $ make -f Makefile.u500vc707devkit mcs
  68 ```
  69
  70 These will place the files under `builds/u500vc707devkit`.
  71
  72 Note that in order to run the `mcs` target, you need to have the `vivado`
  73 executable on your `PATH`.
  74
  75 ### Bootrom
  76
  77 The default bootrom consists of a bootloader that loads a program off the SD
  78 card slot on the VC707 board.