u500: disable PCIe
[freedom-sifive.git] / README.md
1 Freedom
2 =======
3
4 This repository contains the RTL created by SiFive for its Freedom E300 and U500
5 platforms. The Freedom E310 Arty FPGA Dev Kit implements the Freedom E300
6 Platform and is designed to be mapped onto an [Arty FPGA Evaluation
7 Kit](https://www.xilinx.com/products/boards-and-kits/arty.html). The Freedom
8 U500 VC707 FPGA Dev Kit implements the Freedom U500 Platform and is designed to
9 be mapped onto a [VC707 FPGA Evaluation
10 Kit](https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.html).
11 Both systems boot autonomously and can be controlled via an external debugger.
12
13 Please read the section corresponding to the kit you are interested in for
14 instructions on how to use this repo.
15
16 Software Requirement
17 --------------------
18
19 To compile the bootloaders for both Freedom E300 Arty and U500 VC707
20 FPGA dev kits, the RISC-V software toolchain must be installed locally and
21 set the $(RISCV) environment variable to point to the location of where the
22 RISC-V toolchains are installed. You can build the toolchain from scratch
23 or download the tools here: https://www.sifive.com/products/tools/
24
25
26 Freedom E300 Arty FPGA Dev Kit
27 ------------------------------
28
29 The Freedom E300 Arty FPGA Dev Kit implements a Freedom E300 chip.
30
31 ### How to build
32
33 The Makefile corresponding to the Freedom E300 Arty FPGA Dev Kit is
34 `Makefile.e300artydevkit` and it consists of two main targets:
35
36 - `verilog`: to compile the Chisel source files and generate the Verilog files.
37 - `mcs`: to create a Configuration Memory File (.mcs) that can be programmed
38 onto an Arty FPGA board.
39
40 To execute these targets, you can run the following commands:
41
42 ```sh
43 $ make -f Makefile.e300artydevkit verilog
44 $ make -f Makefile.e300artydevkit mcs
45 ```
46
47 Note: This flow requires vivado 2017.1. Old versions are known to fail.
48
49 These will place the files under `builds/e300artydevkit/obj`.
50
51 Note that in order to run the `mcs` target, you need to have the `vivado`
52 executable on your `PATH`.
53
54 ### Bootrom
55
56 The default bootrom consists of a program that immediately jumps to address
57 0x20400000, which is 0x00400000 bytes into the SPI flash memory on the Arty
58 board.
59
60 ### Using the generated MCS Image
61
62 For instructions for getting the generated image onto an FPGA and programming it with software using the [Freedom E SDK](https://github.com/sifive/freedom-e-sdk), please see the [Freedom E310 Arty FPGA Dev Kit Getting Started Guide](https://www.sifive.com/documentation/freedom-soc/freedom-e300-arty-fpga-dev-kit-getting-started-guide/).
63
64 Freedom U500 VC707 FPGA Dev Kit
65 -------------------------------
66
67 The Freedom U500 VC707 FPGA Dev Kit implements the Freedom U500 platform.
68
69 ### How to build
70
71 The Makefile corresponding to the Freedom U500 VC707 FPGA Dev Kit is
72 `Makefile.u500vc707devkit` and it consists of two main targets:
73
74 - `verilog`: to compile the Chisel source files and generate the Verilog files.
75 - `mcs`: to create a Configuration Memory File (.mcs) that can be programmed
76 onto an VC707 FPGA board.
77
78 To execute these targets, you can run the following commands:
79
80 ```sh
81 $ make -f Makefile.u500vc707devkit verilog
82 $ make -f Makefile.u500vc707devkit mcs
83 ```
84
85 Note: This flow requires vivado 2016.1. Newer versions are known to fail.
86
87 These will place the files under `builds/u500vc707devkit/obj`.
88
89 Note that in order to run the `mcs` target, you need to have the `vivado`
90 executable on your `PATH`.
91
92 ### Bootrom
93
94 The default bootrom consists of a bootloader that loads a program off the SD
95 card slot on the VC707 board.