common.mk

   1 # See LICENSE for license details.
   2
   3 # Required variables:
   4 # - MODEL
   5 # - PROJECT
   6 # - CONFIG_PROJECT
   7 # - CONFIG
   8 # - BUILD_DIR
   9 # - FPGA_DIR
  10
  11 # Optional variables:
  12 # - EXTRA_FPGA_VSRCS
  13
  14 EXTRA_FPGA_VSRCS ?=
  15 PATCHVERILOG ?= ""
  16
  17 base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
  18 rocketchip_dir := $(base_dir)/rocket-chip
  19 SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar
  20
  21 # Build firrtl.jar and put it where chisel3 can find it.
  22 FIRRTL_JAR ?= $(rocketchip_dir)/firrtl/utils/bin/firrtl.jar
  23 FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver
  24
  25 $(FIRRTL_JAR): $(shell find $(rocketchip_dir)/firrtl/src/main/scala -iname "*.scala")
  26         $(MAKE) -C $(rocketchip_dir)/firrtl SBT="$(SBT)" root_dir=$(rocketchip_dir)/firrtl build-scala
  27         touch $(FIRRTL_JAR)
  28         mkdir -p $(rocketchip_dir)/chisel3/lib
  29         cp -p $(FIRRTL_JAR) $(rocketchip_dir)/chisel3/lib
  30
  31 # Build .fir
  32 firrtl := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).fir
  33 firrtl_prm := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).prm
  34 $(firrtl) $(firrtl_prm): $(shell find $(base_dir)/src/main/scala -name '*.scala') $(FIRRTL_JAR)
  35         mkdir -p $(dir $@)
  36         $(SBT) "run-main rocketchip.Generator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)"
  37
  38 .PHONY: firrtl
  39 firrtl: $(firrtl)
  40
  41 # Build .v
  42 verilog := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
  43 $(verilog): $(firrtl) $(FIRRTL_JAR)
  44         $(FIRRTL) -i $(firrtl) -o $@ -X verilog
  45 ifneq ($(PATCHVERILOG),"")
  46         $(PATCHVERILOG)
  47 endif
  48
  49
  50 verilog_consts_vh := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vh
  51 $(verilog_consts_vh): $(firrtl_prm)
  52         echo "\`ifndef CONST_VH" > $@
  53         echo "\`define CONST_VH" >> $@
  54         sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $< >> $@
  55         echo "\`endif // CONST_VH" >> $@
  56
  57 .PHONY: verilog
  58 verilog: $(verilog) $(verilog_consts_vh)
  59
  60 # Build .mcs
  61 mcs := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).mcs
  62 $(mcs): $(verilog) $(verilog_consts_vh)
  63         VSRC_TOP=$(verilog) VSRC_CONSTS=$(verilog_consts_vh) EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) mcs
  64         cp $(FPGA_DIR)/obj/system.mcs $@
  65
  66 .PHONY: mcs
  67 mcs: $(mcs)
  68
  69 # Clean
  70 .PHONY: clean
  71 clean:
  72         $(MAKE) -C $(FPGA_DIR) clean
  73         rm -rf $(BUILD_DIR)