common.mk

   1 # See LICENSE for license details.
   2
   3 # Required variables:
   4 # - MODEL
   5 # - PROJECT
   6 # - CONFIG_PROJECT
   7 # - CONFIG
   8 # - BUILD_DIR
   9 # - FPGA_DIR
  10
  11 # Optional variables:
  12 # - EXTRA_FPGA_VSRCS
  13
  14 EXTRA_FPGA_VSRCS ?=
  15 PATCHVERILOG ?= ""
  16
  17 base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
  18 rocketchip_dir := $(base_dir)/rocket-chip
  19 SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar
  20
  21 # Build firrtl.jar and put it where chisel3 can find it.
  22 FIRRTL_JAR ?= $(rocketchip_dir)/firrtl/utils/bin/firrtl.jar
  23 FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver
  24
  25 $(FIRRTL_JAR): $(shell find $(rocketchip_dir)/firrtl/src/main/scala -iname "*.scala")
  26         $(MAKE) -C $(rocketchip_dir)/firrtl SBT="$(SBT)" root_dir=$(rocketchip_dir)/firrtl build-scala
  27         touch $(FIRRTL_JAR)
  28         mkdir -p $(rocketchip_dir)/chisel3/lib
  29         cp -p $(FIRRTL_JAR) $(rocketchip_dir)/chisel3/lib
  30
  31 # Build .fir
  32 firrtl := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).fir
  33 $(firrtl): $(shell find $(base_dir)/src/main/scala -name '*.scala') $(FIRRTL_JAR)
  34         mkdir -p $(dir $@)
  35         $(SBT) "run-main rocketchip.Generator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)"
  36
  37 .PHONY: firrtl
  38 firrtl: $(firrtl)
  39
  40 # Build .v
  41 verilog := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
  42 $(verilog): $(firrtl) $(FIRRTL_JAR)
  43         $(FIRRTL) -i $(firrtl) -o $@ -X verilog
  44 ifneq ($(PATCHVERILOG),"")
  45         $(PATCHVERILOG)
  46 endif
  47
  48
  49 .PHONY: verilog
  50 verilog: $(verilog)
  51
  52 # Build .mcs
  53 mcs := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).mcs
  54 $(mcs): $(verilog)
  55         VSRC_TOP=$(verilog) EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) mcs
  56         cp $(FPGA_DIR)/obj/system.mcs $@
  57
  58 .PHONY: mcs
  59 mcs: $(mcs)
  60
  61 # Clean
  62 .PHONY: clean
  63 clean:
  64         $(MAKE) -C $(FPGA_DIR) clean
  65         rm -rf $(BUILD_DIR)