fpga/u500vc707devkit/constrs/vc707-master.xdc

   1 #---------------Physical Constraints-----------------
   2
   3 set_property BOARD_PIN {clk_p} [get_ports sys_diff_clock_clk_p]
   4 set_property BOARD_PIN {clk_n} [get_ports sys_diff_clock_clk_n]
   5 set_property BOARD_PIN {reset} [get_ports reset]
   6
   7 # The MIG has its own create_clock
   8 #create_clock -name ddr_ref_clk -period 5.0 [get_ports sys_diff_clock_clk_p]
   9 set_input_jitter [get_clocks -of_objects [get_ports sys_diff_clock_clk_p]] 0.5
  10
  11 set_property BOARD_PIN {leds_8bits_tri_o_0} [get_ports led[0]]
  12 set_property BOARD_PIN {leds_8bits_tri_o_1} [get_ports led[1]]
  13 set_property BOARD_PIN {leds_8bits_tri_o_2} [get_ports led[2]]
  14 set_property BOARD_PIN {leds_8bits_tri_o_3} [get_ports led[3]]
  15 set_property BOARD_PIN {leds_8bits_tri_o_4} [get_ports led[4]]
  16 set_property BOARD_PIN {leds_8bits_tri_o_5} [get_ports led[5]]
  17 set_property BOARD_PIN {leds_8bits_tri_o_6} [get_ports led[6]]
  18 set_property BOARD_PIN {leds_8bits_tri_o_7} [get_ports led[7]]
  19
  20 set_property PACKAGE_PIN AU33 [get_ports uart_rx]
  21 set_property IOSTANDARD LVCMOS18 [get_ports uart_rx]
  22 set_property IOB TRUE [get_ports uart_rx]
  23 set_property PACKAGE_PIN AT32 [get_ports uart_ctsn]
  24 set_property IOSTANDARD LVCMOS18 [get_ports uart_ctsn]
  25 set_property IOB TRUE [get_ports uart_ctsn]
  26 set_property PACKAGE_PIN AU36 [get_ports uart_tx]
  27 set_property IOSTANDARD LVCMOS18 [get_ports uart_tx]
  28 set_property IOB TRUE [get_ports uart_tx]
  29 set_property PACKAGE_PIN AR34 [get_ports uart_rtsn]
  30 set_property IOSTANDARD LVCMOS18 [get_ports uart_rtsn]
  31 set_property IOB TRUE [get_ports uart_rtsn]
  32
  33 set_property IOB TRUE [get_cells "top/uart0/txm/out_reg"]
  34 set_property IOB TRUE [get_cells "uart_rx_sync_reg[0]"]
  35
  36
  37 # PCI Express
  38 #FMC 1 refclk
  39 #set_property IOSTANDARD DIFF_HSTL_II_18 [get_ports {pci_exp_refclk_rxp}]
  40 set_property PACKAGE_PIN A10 [get_ports {pci_exp_refclk_rxp}]
  41 set_property PACKAGE_PIN A9 [get_ports {pci_exp_refclk_rxn}]
  42 create_clock -name pcie_ref_clk -period 10 [get_ports pci_exp_refclk_rxp]
  43 set_input_jitter [get_clocks -of_objects [get_ports pci_exp_refclk_rxp]] 0.5
  44
  45 set_property PACKAGE_PIN H4 [get_ports {pci_exp_txp[0]}]
  46 set_property PACKAGE_PIN H3 [get_ports {pci_exp_txn[0]}]
  47
  48 set_property PACKAGE_PIN G6 [get_ports {pci_exp_rxp[0]}]
  49 set_property PACKAGE_PIN G5 [get_ports {pci_exp_rxn[0]}]
  50
  51 # JTAG
  52 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]
  53 set_property -dict { PACKAGE_PIN R32  IOSTANDARD LVCMOS18  PULLUP TRUE } [get_ports {jtag_TCK}]
  54 set_property -dict { PACKAGE_PIN W36  IOSTANDARD LVCMOS18  PULLUP TRUE } [get_ports {jtag_TMS}]
  55 set_property -dict { PACKAGE_PIN W37  IOSTANDARD LVCMOS18  PULLUP TRUE } [get_ports {jtag_TDI}]
  56 set_property -dict { PACKAGE_PIN V40  IOSTANDARD LVCMOS18  PULLUP TRUE } [get_ports {jtag_TDO}]
  57
  58 # SDIO
  59 #set_property -dict { PACKAGE_PIN AR32  IOSTANDARD LVCMOS18 } [get_ports {sdio_sdwp}]
  60 #set_property -dict { PACKAGE_PIN AP32  IOSTANDARD LVCMOS18 } [get_ports {sdio_sddet}]
  61 set_property -dict { PACKAGE_PIN AN30  IOSTANDARD LVCMOS18  IOB TRUE } [get_ports {sdio_clk}]
  62 set_property -dict { PACKAGE_PIN AP30  IOSTANDARD LVCMOS18  IOB TRUE  PULLUP TRUE } [get_ports {sdio_cmd}]
  63 set_property -dict { PACKAGE_PIN AR30  IOSTANDARD LVCMOS18  IOB TRUE  PULLUP TRUE } [get_ports {sdio_dat[0]}]
  64 set_property -dict { PACKAGE_PIN AU31  IOSTANDARD LVCMOS18  IOB TRUE  PULLUP TRUE } [get_ports {sdio_dat[1]}]
  65 set_property -dict { PACKAGE_PIN AV31  IOSTANDARD LVCMOS18  IOB TRUE  PULLUP TRUE } [get_ports {sdio_dat[2]}]
  66 set_property -dict { PACKAGE_PIN AT30  IOSTANDARD LVCMOS18  IOB TRUE  PULLUP TRUE } [get_ports {sdio_dat[3]}]
  67
  68 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/blk_lnk_up"]
  69 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/blk_lnk_up_d"]
  70 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/read_reqSM_cs*"]
  71 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/pcie_bme"]
  72 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/s_axi_arvalid"]
  73 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/arready_int"]
  74 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/en_barhit"]
  75 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/read_reqSM_ns*"]
  76 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/illegal_burst_int"]
  77 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/read_req_sent"]
  78 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/slot_request"]
  79 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/open_slot"]
  80 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/s_axi_arvalid"]
  81
  82 #set_property MARK_DEBUG TRUE [get_nets "top/uncore/outmemsys/L2BroadcastHub_1/BufferedBroadcastAcquireTracker_2/state*"]
  83 #set_property MARK_DEBUG TRUE [get_nets "top/uncore/outmemsys/L2BroadcastHub_1/BufferedBroadcastAcquireTracker_1_1/*acquire*"]
  84 #set_property MARK_DEBUG TRUE [get_nets "top/uncore/outmemsys/L2BroadcastHub_1/io_*"]
  85
  86 set_clock_groups -asynchronous \
  87   -group [list \
  88      [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name =~ *pcie*TXOUTCLK}]]] \
  89   -group [list \
  90      [get_clocks -include_generated_clocks -of_objects [get_ports sys_diff_clock_clk_p]]]