2 create_ip
-vendor xilinx.com
-library ip
-name mig_7series
-module_name vc707mig
-dir $ipdir -force
3 set migprj
[file join [pwd] $scriptdir {mig.prj
}]
4 set_property CONFIG.XML_INPUT_FILE
$migprj [get_ips vc707mig
]
6 puts "SCRIPTDIR $scriptdir"
9 create_ip
-vendor xilinx.com
-library ip
-version 2.8 -name axi_pcie
-module_name vc707axi_to_pcie_x1
-dir $ipdir -force
10 set_property
-dict [list \
11 CONFIG.AXIBAR2PCIEBAR_0
{0x60000000} \
12 CONFIG.AXIBAR2PCIEBAR_1
{0x00000000} \
13 CONFIG.AXIBAR2PCIEBAR_2
{0x00000000} \
14 CONFIG.AXIBAR2PCIEBAR_3
{0x00000000} \
15 CONFIG.AXIBAR2PCIEBAR_4
{0x00000000} \
16 CONFIG.AXIBAR2PCIEBAR_5
{0x00000000} \
17 CONFIG.AXIBAR_0
{0x60000000} \
18 CONFIG.AXIBAR_1
{0xFFFFFFFF} \
19 CONFIG.AXIBAR_2
{0xFFFFFFFF} \
20 CONFIG.AXIBAR_3
{0xFFFFFFFF} \
21 CONFIG.AXIBAR_4
{0xFFFFFFFF} \
22 CONFIG.AXIBAR_5
{0xFFFFFFFF} \
23 CONFIG.AXIBAR_AS_0
{true
} \
24 CONFIG.AXIBAR_AS_1
{false
} \
25 CONFIG.AXIBAR_AS_2
{false
} \
26 CONFIG.AXIBAR_AS_3
{false
} \
27 CONFIG.AXIBAR_AS_4
{false
} \
28 CONFIG.AXIBAR_AS_5
{false
} \
29 CONFIG.AXIBAR_HIGHADDR_0
{0x7FFFFFFF} \
30 CONFIG.AXIBAR_HIGHADDR_1
{0x00000000} \
31 CONFIG.AXIBAR_HIGHADDR_2
{0x00000000} \
32 CONFIG.AXIBAR_HIGHADDR_3
{0x00000000} \
33 CONFIG.AXIBAR_HIGHADDR_4
{0x00000000} \
34 CONFIG.AXIBAR_HIGHADDR_5
{0x00000000} \
35 CONFIG.AXIBAR_NUM
{1} \
36 CONFIG.BAR0_ENABLED
{true
} \
37 CONFIG.BAR0_SCALE
{Gigabytes
} \
38 CONFIG.BAR0_SIZE
{4} \
39 CONFIG.BAR0_TYPE
{Memory
} \
40 CONFIG.BAR1_ENABLED
{false
} \
41 CONFIG.BAR1_SCALE
{N
/A
} \
42 CONFIG.BAR1_SIZE
{8} \
43 CONFIG.BAR1_TYPE
{N
/A
} \
44 CONFIG.BAR2_ENABLED
{false
} \
45 CONFIG.BAR2_SCALE
{N
/A
} \
46 CONFIG.BAR2_SIZE
{8} \
47 CONFIG.BAR2_TYPE
{N
/A
} \
48 CONFIG.BAR_64BIT
{true
} \
49 CONFIG.BASEADDR
{0x50000000} \
50 CONFIG.BASE_CLASS_MENU
{Bridge_device
} \
51 CONFIG.CLASS_CODE
{0x060400} \
52 CONFIG.COMP_TIMEOUT
{50us
} \
53 CONFIG.Component_Name
{design_1_axi_pcie_1_0
} \
54 CONFIG.DEVICE_ID
{0x7111} \
55 CONFIG.ENABLE_CLASS_CODE
{true
} \
56 CONFIG.HIGHADDR
{0x53FFFFFF} \
57 CONFIG.INCLUDE_BAROFFSET_REG
{true
} \
58 CONFIG.INCLUDE_RC
{Root_Port_of_PCI_Express_Root_Complex
} \
59 CONFIG.INTERRUPT_PIN
{false
} \
60 CONFIG.MAX_LINK_SPEED
{2.5_GT
/s
} \
61 CONFIG.MSI_DECODE_ENABLED
{true
} \
62 CONFIG.M_AXI_ADDR_WIDTH
{32} \
63 CONFIG.M_AXI_DATA_WIDTH
{64} \
64 CONFIG.NO_OF_LANES
{X1
} \
65 CONFIG.NUM_MSI_REQ
{0} \
66 CONFIG.PCIEBAR2AXIBAR_0_SEC
{1} \
67 CONFIG.PCIEBAR2AXIBAR_0
{0x00000000} \
68 CONFIG.PCIEBAR2AXIBAR_1
{0xFFFFFFFF} \
69 CONFIG.PCIEBAR2AXIBAR_1_SEC
{1} \
70 CONFIG.PCIEBAR2AXIBAR_2
{0xFFFFFFFF} \
71 CONFIG.PCIEBAR2AXIBAR_2_SEC
{1} \
72 CONFIG.PCIE_BLK_LOCN
{X1Y1
} \
73 CONFIG.PCIE_USE_MODE
{GES_and_Production
} \
74 CONFIG.REF_CLK_FREQ
{100_MHz
} \
75 CONFIG.REV_ID
{0x00} \
76 CONFIG.SLOT_CLOCK_CONFIG
{true
} \
77 CONFIG.SUBSYSTEM_ID
{0x0007} \
78 CONFIG.SUBSYSTEM_VENDOR_ID
{0x10EE} \
79 CONFIG.SUB_CLASS_INTERFACE_MENU
{Host_bridge
} \
80 CONFIG.S_AXI_ADDR_WIDTH
{32} \
81 CONFIG.S_AXI_DATA_WIDTH
{64} \
82 CONFIG.S_AXI_ID_WIDTH
{4} \
83 CONFIG.S_AXI_SUPPORTS_NARROW_BURST
{false
} \
84 CONFIG.VENDOR_ID
{0x10EE} \
85 CONFIG.XLNX_REF_BOARD
{None
} \
86 CONFIG.axi_aclk_loopback
{false
} \
87 CONFIG.en_ext_ch_gt_drp
{false
} \
88 CONFIG.en_ext_clk
{false
} \
89 CONFIG.en_ext_gt_common
{false
} \
90 CONFIG.en_ext_pipe_interface
{false
} \
91 CONFIG.en_transceiver_status_ports
{false
} \
92 CONFIG.no_slv_err
{false
} \
93 CONFIG.rp_bar_hide
{true
} \
94 CONFIG.shared_logic_in_core
{false
} ] [get_ips vc707axi_to_pcie_x1
]