src/main/scala/everywhere/e300artydevkit/Platform.scala

   1 // See LICENSE for license details.
   2 package sifive.freedom.everywhere.e300artydevkit
   3
   4 import Chisel._
   5
   6 import freechips.rocketchip.config._
   7 import freechips.rocketchip.coreplex._
   8 import freechips.rocketchip.devices.debug._
   9 import freechips.rocketchip.devices.tilelink._
  10 import freechips.rocketchip.diplomacy._
  11 import freechips.rocketchip.util.ResetCatchAndSync
  12 import freechips.rocketchip.system._
  13
  14 import sifive.blocks.devices.mockaon._
  15 import sifive.blocks.devices.gpio._
  16 import sifive.blocks.devices.jtag._
  17 import sifive.blocks.devices.pwm._
  18 import sifive.blocks.devices.spi._
  19 import sifive.blocks.devices.uart._
  20 import sifive.blocks.devices.i2c._
  21 import sifive.blocks.devices.pinctrl._
  22
  23 //-------------------------------------------------------------------------
  24 // PinGen
  25 //-------------------------------------------------------------------------
  26
  27 object PinGen {
  28   def apply(): BasePin =  {
  29     val pin = new BasePin()
  30     pin
  31   }
  32 }
  33
  34 //-------------------------------------------------------------------------
  35 // E300ArtyDevKitPlatformIO
  36 //-------------------------------------------------------------------------
  37
  38 class E300ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle {
  39   val pins = new Bundle {
  40     val jtag = new JTAGPins(() => PinGen(), false)
  41     val gpio = new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))
  42     val qspi = new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))
  43     val aon = new MockAONWrapperPins()
  44   }
  45   val jtag_reset = Bool(INPUT)
  46   val ndreset    = Bool(OUTPUT)
  47 }
  48
  49 //-------------------------------------------------------------------------
  50 // E300ArtyDevKitPlatform
  51 //-------------------------------------------------------------------------
  52
  53 class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module {
  54   val sys = Module(LazyModule(new E300ArtyDevKitSystem).module)
  55   val io = new E300ArtyDevKitPlatformIO
  56
  57   // This needs to be de-asserted synchronously to the coreClk.
  58   val async_corerst = sys.aon.rsts.corerst
  59   // Add in debug-controlled reset.
  60   sys.reset := ResetCatchAndSync(clock, async_corerst, 20)
  61
  62   //-----------------------------------------------------------------------
  63   // Check for unsupported rocket-chip connections
  64   //-----------------------------------------------------------------------
  65
  66   require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported");
  67
  68   //-----------------------------------------------------------------------
  69   // Build GPIO Pin Mux
  70   //-----------------------------------------------------------------------
  71   // Pin Mux for UART, SPI, PWM
  72   // First convert the System outputs into "IOF" using the respective *GPIOPort
  73   // converters.
  74
  75   val sys_uart = sys.uart
  76   val sys_pwm  = sys.pwm
  77   val sys_spi  = sys.spi
  78   val sys_i2c  = sys.i2c
  79
  80   val uart_pins = sys.outer.uartParams.map { c => Wire(new UARTPins(() => PinGen()))}
  81   val pwm_pins  = sys.outer.pwmParams.map  { c => Wire(new PWMPins(() => PinGen(), c))}
  82   val spi_pins  = sys.outer.spiParams.map  { c => Wire(new SPIPins(() => PinGen(), c))}
  83   val i2c_pins  = sys.outer.i2cParams.map  { c => Wire(new I2CPins(() => PinGen()))}
  84
  85   (uart_pins zip  sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)}
  86   (pwm_pins  zip  sys_pwm)  map {case (p, r) => PWMPinsFromPort(p, r) }
  87   (spi_pins  zip  sys_spi)  map {case (p, r) => SPIPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)}
  88   (i2c_pins  zip  sys_i2c)  map {case (p, r) => I2CPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)}
  89
  90   //-----------------------------------------------------------------------
  91   // Default Pin connections before attaching pinmux
  92
  93   for (iof_0 <- sys.gpio(0).iof_0.get) {
  94     iof_0.default()
  95   }
  96
  97   for (iof_1 <- sys.gpio(0).iof_1.get) {
  98     iof_1.default()
  99   }
 100
 101   //-----------------------------------------------------------------------
 102
 103   val iof_0 = sys.gpio(0).iof_0.get
 104   val iof_1 = sys.gpio(0).iof_1.get
 105
 106   // SPI1 (0 is the dedicated)
 107   BasePinToIOF(spi_pins(0).cs(0), iof_0(2))
 108   BasePinToIOF(spi_pins(0).dq(0), iof_0(3))
 109   BasePinToIOF(spi_pins(0).dq(1), iof_0(4))
 110   BasePinToIOF(spi_pins(0).sck,   iof_0(5))
 111   BasePinToIOF(spi_pins(0).dq(2), iof_0(6))
 112   BasePinToIOF(spi_pins(0).dq(3), iof_0(7))
 113   BasePinToIOF(spi_pins(0).cs(1), iof_0(8))
 114   BasePinToIOF(spi_pins(0).cs(2), iof_0(9))
 115   BasePinToIOF(spi_pins(0).cs(3), iof_0(10))
 116
 117   // SPI2
 118   BasePinToIOF(spi_pins(1).cs(0), iof_0(26))
 119   BasePinToIOF(spi_pins(1).dq(0), iof_0(27))
 120   BasePinToIOF(spi_pins(1).dq(1), iof_0(28))
 121   BasePinToIOF(spi_pins(1).sck,   iof_0(29))
 122   BasePinToIOF(spi_pins(1).dq(2), iof_0(30))
 123   BasePinToIOF(spi_pins(1).dq(3), iof_0(31))
 124
 125   // I2C
 126   if (sys.outer.i2cParams.length == 1) {
 127     BasePinToIOF(i2c_pins(0).sda, iof_0(12))
 128     BasePinToIOF(i2c_pins(0).scl, iof_0(13))
 129   }
 130
 131   // UART0
 132   BasePinToIOF(uart_pins(0).rxd, iof_0(16))
 133   BasePinToIOF(uart_pins(0).txd, iof_0(17))
 134
 135   // UART1
 136   BasePinToIOF(uart_pins(1).rxd, iof_0(24))
 137   BasePinToIOF(uart_pins(1).txd, iof_0(25))
 138
 139   //PWM
 140   BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) )
 141   BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) )
 142   BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) )
 143   BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) )
 144
 145   BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19))
 146   BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20))
 147   BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21))
 148   BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22))
 149
 150   BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10))
 151   BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11))
 152   BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12))
 153   BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13))
 154
 155   //-----------------------------------------------------------------------
 156   // Drive actual Pads
 157   //-----------------------------------------------------------------------
 158
 159   // Result of Pin Mux
 160   GPIOPinsFromPort(io.pins.gpio, sys.gpio(0))
 161
 162   // Dedicated SPI Pads
 163   SPIPinsFromPort(io.pins.qspi, sys.qspi(0), clock = sys.clock, reset = sys.reset, syncStages = 3)
 164
 165   // JTAG Debug Interface
 166   val sjtag = sys.debug.systemjtag.get
 167   JTAGPinsFromPort(io.pins.jtag, sjtag.jtag)
 168   sjtag.reset := io.jtag_reset
 169   sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
 170
 171   io.ndreset := sys.debug.ndreset
 172
 173   // AON Pads -- direct connection is OK because
 174   // EnhancedPin is hard-coded in MockAONPads
 175   // and thus there is no .fromPort method.
 176   io.pins.aon <> sys.aon.pins
 177 }