Updates to Freedom SoCs
[freedom-sifive.git] / src / main / scala / unleashed / u500vc707devkit / Config.scala
1 // See LICENSE for license details.
2 package sifive.freedom.unleashed.u500vc707devkit
3
4 import freechips.rocketchip.config._
5 import freechips.rocketchip.coreplex._
6 import freechips.rocketchip.devices.debug._
7 import freechips.rocketchip.devices.tilelink._
8 import freechips.rocketchip.diplomacy._
9 import freechips.rocketchip.system._
10 import freechips.rocketchip.tile._
11
12 import sifive.blocks.devices.gpio._
13 import sifive.blocks.devices.spi._
14 import sifive.blocks.devices.uart._
15
16 // Default FreedomUVC707Config
17 class FreedomUVC707Config extends Config(
18 new WithJtagDTM ++
19 new WithNMemoryChannels(1) ++
20 new WithNBigCores(1) ++
21 new BaseConfig
22 )
23
24 // Freedom U500 VC707 Dev Kit Peripherals
25 class U500VC707DevKitPeripherals extends Config((site, here, up) => {
26 case PeripheryUARTKey => List(
27 UARTParams(address = BigInt(0x54000000L)))
28 case PeripherySPIKey => List(
29 SPIParams(rAddress = BigInt(0x54001000L)))
30 case PeripheryGPIOKey => List(
31 GPIOParams(address = BigInt(0x54002000L), width = 4))
32 case PeripheryMaskROMKey => List(
33 MaskROMParams(address = 0x10000, name = "BootROM"))
34 })
35
36 // Freedom U500 VC707 Dev Kit
37 class U500VC707DevKitConfig extends Config(
38 new WithoutFPU ++
39 new WithNExtTopInterrupts(0) ++
40 new U500VC707DevKitPeripherals ++
41 new FreedomUVC707Config().alter((site,here,up) => {
42 case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)))
43 case PeripheryBusParams => up(PeripheryBusParams, site).copy(frequency = 50000000) // 50 MHz hperiphery
44 case DTSTimebase => BigInt(1000000)
45 case ExtMem => up(ExtMem).copy(size = 0x40000000L)
46 case JtagDTMKey => new JtagDTMConfig (
47 idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai).
48 idcodePartNum = 0x000, // Decided to simplify.
49 idcodeManufId = 0x489, // As Assigned by JEDEC to SiFive. Only used in wrappers / test harnesses.
50 debugIdleCycles = 5) // Reasonable guess for synchronization
51 })
52 )