1 // See LICENSE for license details.
2 package sifive.freedom.unleashed.u500vc707devkit
5 import chisel3.experimental.{withClockAndReset}
7 import freechips.rocketchip.config._
8 import freechips.rocketchip.diplomacy._
10 import sifive.blocks.devices.gpio._
11 import sifive.blocks.devices.pinctrl.{BasePin}
13 import sifive.fpgashells.shell.xilinx.vc707shell._
14 import sifive.fpgashells.ip.xilinx.{IOBUF}
16 //-------------------------------------------------------------------------
18 //-------------------------------------------------------------------------
21 def apply(): BasePin = {
26 //-------------------------------------------------------------------------
27 // U500VC707DevKitFPGAChip
28 //-------------------------------------------------------------------------
30 class U500VC707DevKitFPGAChip(implicit override val p: Parameters)
34 //-----------------------------------------------------------------------
36 //-----------------------------------------------------------------------
38 // Connect the clock to the 50 Mhz output from the PLL
40 withClockAndReset(dut_clock, dut_reset) {
41 val dut = Module(LazyModule(new U500VC707DevKitSystem).module)
43 //---------------------------------------------------------------------
44 // Connect peripherals
45 //---------------------------------------------------------------------
52 //---------------------------------------------------------------------
54 //---------------------------------------------------------------------
56 val gpioParams = p(PeripheryGPIOKey)
57 val gpio_pins = Wire(new GPIOPins(() => PinGen(), gpioParams(0)))
59 GPIOPinsFromPort(gpio_pins, dut.gpio(0))
61 gpio_pins.pins.foreach { _.i.ival := Bool(false) }
62 gpio_pins.pins.zipWithIndex.foreach {
63 case(pin, idx) => led(idx) := pin.o.oval
67 for( idx <- 7 to 4 ) { led(idx) := false.B }