# See LICENSE for license details. # Required variables: # - MODEL # - PROJECT # - CONFIG_PROJECT # - CONFIG # - BUILD_DIR # - FPGA_DIR # Optional variables: # - EXTRA_FPGA_VSRCS # export to bootloader export ROMCONF=$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.conf # export to fpga-shells export FPGA_TOP_SYSTEM=$(MODEL) export FPGA_BUILD_DIR=$(BUILD_DIR)/$(FPGA_TOP_SYSTEM) export fpga_common_script_dir=$(FPGA_DIR)/common/tcl export fpga_board_script_dir=$(FPGA_DIR)/$(BOARD)/tcl export BUILD_DIR EXTRA_FPGA_VSRCS ?= PATCHVERILOG ?= "" BOOTROM_DIR ?= "" base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))) export rocketchip_dir := $(base_dir)/rocket-chip SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar # Build firrtl.jar and put it where chisel3 can find it. FIRRTL_JAR ?= $(rocketchip_dir)/firrtl/utils/bin/firrtl.jar FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver $(FIRRTL_JAR): $(shell find $(rocketchip_dir)/firrtl/src/main/scala -iname "*.scala") $(MAKE) -C $(rocketchip_dir)/firrtl SBT="$(SBT)" root_dir=$(rocketchip_dir)/firrtl build-scala touch $(FIRRTL_JAR) mkdir -p $(rocketchip_dir)/lib cp -p $(FIRRTL_JAR) rocket-chip/lib mkdir -p $(rocketchip_dir)/chisel3/lib cp -p $(FIRRTL_JAR) $(rocketchip_dir)/chisel3/lib # Build .fir firrtl := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).fir $(firrtl): $(shell find $(base_dir)/src/main/scala -name '*.scala') $(FIRRTL_JAR) mkdir -p $(dir $@) $(SBT) "run-main freechips.rocketchip.system.Generator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)" .PHONY: firrtl firrtl: $(firrtl) # Build .v verilog := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v $(verilog): $(firrtl) $(FIRRTL_JAR) $(FIRRTL) -i $(firrtl) -o $@ -X verilog ifneq ($(PATCHVERILOG),"") $(PATCHVERILOG) endif .PHONY: verilog verilog: $(verilog) romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v $(romgen): $(verilog) ifneq ($(BOOTROM_DIR),"") $(MAKE) -C $(BOOTROM_DIR) romgen mv $(BUILD_DIR)/rom.v $@ endif .PHONY: romgen romgen: $(romgen) f := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F $(f): echo $(VSRCS) > $@ bit := $(BUILD_DIR)/obj/$(MODEL).bit $(bit): $(romgen) $(f) cd $(BUILD_DIR); vivado \ -nojournal -mode batch \ -source $(fpga_common_script_dir)/vivado.tcl \ -tclargs \ -top-module "$(MODEL)" \ -F "$(f)" \ -ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \ -board "$(BOARD)" # Build .mcs mcs := $(BUILD_DIR)/obj/$(MODEL).mcs $(mcs): $(bit) cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $< .PHONY: mcs mcs: $(mcs) # Clean .PHONY: clean clean: ifneq ($(BOOTROM_DIR),"") $(MAKE) -C $(BOOTROM_DIR) clean endif $(MAKE) -C $(FPGA_DIR) clean rm -rf $(BUILD_DIR)