README: update location of built files

[freedom-sifive.git] / Makefile.e300artydevkit

diff --git a/Makefile.e300artydevkit b/Makefile.e300artydevkit
index 0e033191d3f77c3d103233c30f934f77bb2fc471..04b0af5b0099240409409e366b0511ea77ade6bb 100644 (file)
--- a/Makefile.e300artydevkit
+++ b/Makefile.e300artydevkit
@@ -1,17 +1,22 @@
 # See LICENSE for license details.
 base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
 BUILD_DIR := $(base_dir)/builds/e300artydevkit
-FPGA_DIR := $(base_dir)/fpga/e300artydevkit
-MODEL := E300ArtyDevKitTop
+FPGA_DIR := $(base_dir)/fpga-shells/xilinx
+MODEL := E300ArtyDevKitFPGAChip
 PROJECT := sifive.freedom.everywhere.e300artydevkit
 CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit
-CONFIG := E300ArtyDevKitConfig
+export CONFIG := E300ArtyDevKitConfig
+export BOARD := arty
+export BOOTROM_DIR := $(base_dir)/bootrom/xip
 
 rocketchip_dir := $(base_dir)/rocket-chip
 sifiveblocks_dir := $(base_dir)/sifive-blocks
-EXTRA_FPGA_VSRCS := \
+VSRCS := \
        $(rocketchip_dir)/vsrc/AsyncResetReg.v \
-       $(rocketchip_dir)/vsrc/DebugTransportModuleJtag.v \
-       $(sifiveblocks_dir)/vsrc/SRLatch.v
+       $(rocketchip_dir)/vsrc/plusarg_reader.v \
+       $(sifiveblocks_dir)/vsrc/SRLatch.v \
+       $(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
+       $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
+       $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
 
 include common.mk