u500: disable PCIe

[freedom-sifive.git] / README.md

diff --git a/README.md b/README.md
index db2a2168e1c7ad63bc2f2f584f77af1408a3ebb3..f1d22ac0ea74e5aa5c748fa1e594846fe66ac65c 100644 (file)
--- a/README.md
+++ b/README.md
@@ -8,19 +8,29 @@ Kit](https://www.xilinx.com/products/boards-and-kits/arty.html). The Freedom
 U500 VC707 FPGA Dev Kit implements the Freedom U500 Platform and is designed to
 be mapped onto a [VC707 FPGA Evaluation
 Kit](https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.html).
+Both systems boot autonomously and can be controlled via an external debugger.
 
 Please read the section corresponding to the kit you are interested in for
 instructions on how to use this repo.
 
+Software Requirement
+--------------------
 
-Freedom E310 Arty FPGA Dev Kit
+To compile the bootloaders for both Freedom E300 Arty and U500 VC707
+FPGA dev kits, the RISC-V software toolchain must be installed locally and
+set the $(RISCV) environment variable to point to the location of where the
+RISC-V toolchains are installed. You can build the toolchain from scratch
+or download the tools here: https://www.sifive.com/products/tools/
+
+
+Freedom E300 Arty FPGA Dev Kit
 ------------------------------
 
-The Freedom E310 Arty FPGA Dev Kit implements a Freedom E310 chip.
+The Freedom E300 Arty FPGA Dev Kit implements a Freedom E300 chip.
 
 ### How to build
 
-The Makefile corresponding to the Freedom E310 Arty FPGA Dev Kit is
+The Makefile corresponding to the Freedom E300 Arty FPGA Dev Kit is
 `Makefile.e300artydevkit` and it consists of two main targets:
 
 - `verilog`: to compile the Chisel source files and generate the Verilog files.
@@ -34,7 +44,9 @@ $ make -f Makefile.e300artydevkit verilog
 $ make -f Makefile.e300artydevkit mcs
 ```
 
-These will place the files under `builds/e300artydevkit`.
+Note: This flow requires vivado 2017.1. Old versions are known to fail.
+
+These will place the files under `builds/e300artydevkit/obj`.
 
 Note that in order to run the `mcs` target, you need to have the `vivado`
 executable on your `PATH`.
@@ -45,6 +57,9 @@ The default bootrom consists of a program that immediately jumps to address
 0x20400000, which is 0x00400000 bytes into the SPI flash memory on the Arty
 board.
 
+### Using the generated MCS Image
+
+For instructions for getting the generated image onto an FPGA and programming it with software using the [Freedom E SDK](https://github.com/sifive/freedom-e-sdk), please see the [Freedom E310 Arty FPGA Dev Kit Getting Started Guide](https://www.sifive.com/documentation/freedom-soc/freedom-e300-arty-fpga-dev-kit-getting-started-guide/).
 
 Freedom U500 VC707 FPGA Dev Kit
 -------------------------------
@@ -67,7 +82,9 @@ $ make -f Makefile.u500vc707devkit verilog
 $ make -f Makefile.u500vc707devkit mcs
 ```
 
-These will place the files under `builds/u500vc707devkit`.
+Note: This flow requires vivado 2016.1. Newer versions are known to fail.
+
+These will place the files under `builds/u500vc707devkit/obj`.
 
 Note that in order to run the `mcs` target, you need to have the `vivado`
 executable on your `PATH`.