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Remove verilog header files built from Chisel .prm file.
[freedom-sifive.git]
/
fpga
/
e300artydevkit
/
src
/
system.v
diff --git
a/fpga/e300artydevkit/src/system.v
b/fpga/e300artydevkit/src/system.v
index 1c45c43e40da1a3fcf14e25b2598fa08b95a217d..afb40d5d59cc562e51097b1b3a4f4ebc712fb27f 100644
(file)
--- a/
fpga/e300artydevkit/src/system.v
+++ b/
fpga/e300artydevkit/src/system.v
@@
-1,8
+1,5
@@
`timescale 1ns/1ps
-`define STRINGIFY(x) `"x`"
-`include `STRINGIFY(`VSRC_CONSTS)
-
module system
(
input wire CLK100MHZ,