Remove verilog header files built from Chisel .prm file.

[freedom-sifive.git] / fpga / u500vc707devkit / src / system.v

diff --git a/fpga/u500vc707devkit/src/system.v b/fpga/u500vc707devkit/src/system.v
index e81edcb99bd2e861b1f399a10c1433a09d3da362..fb6ae5b6a4c10e0d35525160ca978ccd06a536b7 100644 (file)
--- a/fpga/u500vc707devkit/src/system.v
+++ b/fpga/u500vc707devkit/src/system.v
@@ -2,9 +2,6 @@
 `timescale 1ns/1ps
 `default_nettype none
 
-`define STRINGIFY(x) `"x`"
-`include `STRINGIFY(`VSRC_CONSTS)
-
 module system
 (
   //200Mhz differential sysclk