Merge pull request #40 from sifive/bump

[freedom-sifive.git] / src / main / scala / unleashed / u500vc707devkit / Config.scala

diff --git a/src/main/scala/unleashed/u500vc707devkit/Config.scala b/src/main/scala/unleashed/u500vc707devkit/Config.scala
index a899e9650612e6c18bc64a5fe1267ac61a536939..4598f2f4dcc49f515cf2a457fd32e0198f0d3214 100644 (file)
--- a/src/main/scala/unleashed/u500vc707devkit/Config.scala
+++ b/src/main/scala/unleashed/u500vc707devkit/Config.scala
@@ -13,11 +13,13 @@ import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.spi._
 import sifive.blocks.devices.uart._
 
+import sifive.fpgashells.devices.xilinx.xilinxvc707mig.{MemoryXilinxDDRKey,XilinxVC707MIGParams}
+
 // Default FreedomUVC707Config
 class FreedomUVC707Config extends Config(
   new WithJtagDTM            ++
   new WithNMemoryChannels(1) ++
-  new WithNBigCores(1)       ++
+  new WithNBigCores(4)       ++
   new BaseConfig
 )
 
@@ -35,12 +37,12 @@ class U500VC707DevKitPeripherals extends Config((site, here, up) => {
 
 // Freedom U500 VC707 Dev Kit
 class U500VC707DevKitConfig extends Config(
-  new WithoutFPU                 ++
   new WithNExtTopInterrupts(0)   ++
   new U500VC707DevKitPeripherals ++
   new FreedomUVC707Config().alter((site,here,up) => {
     case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)))
-    case PeripheryBusParams => up(PeripheryBusParams, site).copy(frequency = 50000000) // 50 MHz hperiphery
+    case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery
+    case MemoryXilinxDDRKey => XilinxVC707MIGParams(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
     case DTSTimebase => BigInt(1000000)
     case ExtMem => up(ExtMem).copy(size = 0x40000000L)
     case JtagDTMKey => new JtagDTMConfig (