X-Git-Url: https://git.libre-soc.org/?p=freedom-sifive.git;a=blobdiff_plain;f=Makefile.u500vc707devkit;h=70692fa7de85f43ddfc54056d6037ec9efd34625;hp=8845eb058437d322da8d2e0451ac72bc2071eb89;hb=e1673b86705f0fc3f812a46bd08c4ae7ff054fa3;hpb=3cf8128a3037cbe02a1542c43f7bf3798f6060b1

diff --git a/Makefile.u500vc707devkit b/Makefile.u500vc707devkit
index 8845eb0..70692fa 100644
--- a/Makefile.u500vc707devkit
+++ b/Makefile.u500vc707devkit
@@ -1,39 +1,24 @@
 # See LICENSE for license details.
 base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
 BUILD_DIR := $(base_dir)/builds/u500vc707devkit
-FPGA_DIR := $(base_dir)/fpga/u500vc707devkit
-MODEL := U500VC707DevKitTop
+FPGA_DIR := $(base_dir)/fpga-shells/xilinx
+MODEL := U500VC707DevKitFPGAChip
 PROJECT := sifive.freedom.unleashed.u500vc707devkit
 CONFIG_PROJECT := sifive.freedom.unleashed.u500vc707devkit
-CONFIG := U500VC707DevKitConfig
+export CONFIG := U500VC707DevKitConfig
+export BOARD := vc707
+export BOOTROM_DIR := $(base_dir)/bootrom/sdboot
 
 rocketchip_dir := $(base_dir)/rocket-chip
 sifiveblocks_dir := $(base_dir)/sifive-blocks
-EXTRA_FPGA_VSRCS := \
+VSRCS := \
 	$(rocketchip_dir)/vsrc/AsyncResetReg.v \
-	$(rocketchip_dir)/vsrc/DebugTransportModuleJtag.v \
+	$(rocketchip_dir)/vsrc/plusarg_reader.v \
 	$(sifiveblocks_dir)/vsrc/SRLatch.v \
-	$(sifiveblocks_dir)/vsrc/vc707reset.v
-
-PATCHVERILOG = \
-sed -i -s "s/ *output\(.*\)__inout\(.*\)/inout \1__inout\2/g" $@ && \
-grep -q -F   "    .io_xilinxvc707mig__inout_ddr3_dq(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dq)," $@ && \
-sed -i -s  "s/    .io_xilinxvc707mig__inout_ddr3_dq(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dq),/    .io_xilinxvc707mig__inout_ddr3_dq(io_xilinxvc707mig__inout_ddr3_dq),/g" $@ && \
-grep -q -F   "    .io_xilinxvc707mig__inout_ddr3_dqs_n(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dqs_n)," $@ && \
-sed -i -s  "s/    .io_xilinxvc707mig__inout_ddr3_dqs_n(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dqs_n),/    .io_xilinxvc707mig__inout_ddr3_dqs_n(io_xilinxvc707mig__inout_ddr3_dqs_n),/g" $@ && \
-grep -q -F   "    .io_xilinxvc707mig__inout_ddr3_dqs_p(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dqs_p)," $@ && \
-sed -i -s  "s/    .io_xilinxvc707mig__inout_ddr3_dqs_p(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dqs_p),/    .io_xilinxvc707mig__inout_ddr3_dqs_p(io_xilinxvc707mig__inout_ddr3_dqs_p),/g" $@ && \
-grep -q -F   "    .io_port__inout_ddr3_dq(xilinxvc707mig_io_port__inout_ddr3_dq)," $@ && \
-sed -i -s  "s/    .io_port__inout_ddr3_dq(xilinxvc707mig_io_port__inout_ddr3_dq),/    .io_port__inout_ddr3_dq(io_xilinxvc707mig__inout_ddr3_dq),/g" $@ && \
-grep -q -F   "    .io_port__inout_ddr3_dqs_n(xilinxvc707mig_io_port__inout_ddr3_dqs_n)," $@ && \
-sed -i -s  "s/    .io_port__inout_ddr3_dqs_n(xilinxvc707mig_io_port__inout_ddr3_dqs_n),/    .io_port__inout_ddr3_dqs_n(io_xilinxvc707mig__inout_ddr3_dqs_n),/g" $@ && \
-grep -q -F   "    .io_port__inout_ddr3_dqs_p(xilinxvc707mig_io_port__inout_ddr3_dqs_p)" $@ && \
-sed -i -s  "s/    .io_port__inout_ddr3_dqs_p(xilinxvc707mig_io_port__inout_ddr3_dqs_p)/    .io_port__inout_ddr3_dqs_p(io_xilinxvc707mig__inout_ddr3_dqs_p)/g" $@ && \
-grep -q -F   "   .ddr3_dq(blackbox_ddr3_dq)," $@ && \
-sed -i -s  "s/   .ddr3_dq(blackbox_ddr3_dq),/   .ddr3_dq(io_port__inout_ddr3_dq),/g" $@ && \
-grep -q -F   "   .ddr3_dqs_n(blackbox_ddr3_dqs_n)," $@ && \
-sed -i -s  "s/   .ddr3_dqs_n(blackbox_ddr3_dqs_n),/   .ddr3_dqs_n(io_port__inout_ddr3_dqs_n),/g" $@ && \
-grep -q -F   "   .ddr3_dqs_p(blackbox_ddr3_dqs_p)," $@ && \
-sed -i -s  "s/   .ddr3_dqs_p(blackbox_ddr3_dqs_p),/   .ddr3_dqs_p(io_port__inout_ddr3_dqs_p),/g" $@ 
+	$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
+	$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
+	$(FPGA_DIR)/$(BOARD)/vsrc/vc707reset.v \
+	$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
+	$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
 
 include common.mk