--- /dev/null
+# See LICENSE for license details.
+base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
+BUILD_DIR := $(base_dir)/builds/ic0artydevkit
+FPGA_DIR := $(base_dir)/fpga-shells/xilinx
+MODEL := IC0ArtyDevKitFPGAChip
+PROJECT := sifive.freedom.shakti.ic0artydevkit
+CONFIG_PROJECT := sifive.freedom.shakti.ic0artydevkit
+export CONFIG := IC0ArtyDevKitConfig
+export BOARD := arty
+export BOOTROM_DIR := $(base_dir)/bootrom/xip
+
+rocketchip_dir := $(base_dir)/rocket-chip
+sifiveblocks_dir := $(base_dir)/sifive-blocks
+VSRCS := \
+ $(rocketchip_dir)/vsrc/AsyncResetReg.v \
+ $(rocketchip_dir)/vsrc/plusarg_reader.v \
+ $(sifiveblocks_dir)/vsrc/SRLatch.v \
+ $(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
+ $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
+ $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
+
+include common.mk
--- /dev/null
+// See LICENSE for license details.
+package sifive.freedom.shakti.ic0artydevkit
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.coreplex._
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase}
+import freechips.rocketchip.system._
+import freechips.rocketchip.tile._
+
+import sifive.blocks.devices.mockaon._
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.pwm._
+import sifive.blocks.devices.spi._
+import sifive.blocks.devices.uart._
+import sifive.blocks.devices.i2c._
+
+// Default ShaktiIClassEConfig
+class DefaultShaktiIClassEConfig extends Config (
+ new WithNBreakpoints(2) ++
+ new WithNExtTopInterrupts(0) ++
+ new WithJtagDTM ++
+ new TinyConfig
+)
+
+// ShaktiIClass IC0 Arty Dev Kit Peripherals
+class IC0DevKitPeripherals extends Config((site, here, up) => {
+ case PeripheryGPIOKey => List(
+ GPIOParams(address = 0x10012000, width = 32, includeIOF = true))
+ case PeripheryPWMKey => List(
+ PWMParams(address = 0x10015000, cmpWidth = 8),
+ PWMParams(address = 0x10025000, cmpWidth = 16),
+ PWMParams(address = 0x10035000, cmpWidth = 16))
+ case PeripherySPIKey => List(
+ SPIParams(csWidth = 4, rAddress = 0x10024000, sampleDelay = 3),
+ SPIParams(csWidth = 1, rAddress = 0x10034000, sampleDelay = 3))
+ case PeripherySPIFlashKey => List(
+ SPIFlashParams(
+ fAddress = 0x20000000,
+ rAddress = 0x10014000,
+ sampleDelay = 3))
+ case PeripheryUARTKey => List(
+ UARTParams(address = 0x10013000),
+ UARTParams(address = 0x10023000))
+ case PeripheryI2CKey => List(
+ I2CParams(address = 0x10016000))
+ case PeripheryMockAONKey =>
+ MockAONParams(address = 0x10000000)
+ case PeripheryMaskROMKey => List(
+ MaskROMParams(address = 0x10000, name = "BootROM"))
+})
+
+// ShaktiIClass IC0 Arty Dev Kit Peripherals
+class IC0ArtyDevKitConfig extends Config(
+ new IC0DevKitPeripherals ++
+ new DefaultShaktiIClassEConfig().alter((site,here,up) => {
+ case DTSTimebase => BigInt(32768)
+ case JtagDTMKey => new JtagDTMConfig (
+ idcodeVersion = 2,
+ idcodePartNum = 0x000,
+ idcodeManufId = 0x489,
+ debugIdleCycles = 5)
+ })
+)
--- /dev/null
+// See LICENSE for license details.
+package sifive.freedom.shakti.ic0artydevkit
+
+import Chisel._
+import chisel3.core.{attach}
+import chisel3.experimental.{withClockAndReset}
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.diplomacy.{LazyModule}
+
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.spi._
+
+import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
+import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
+
+//-------------------------------------------------------------------------
+// IC0ArtyDevKitFPGAChip
+//-------------------------------------------------------------------------
+
+class IC0ArtyDevKitFPGAChip(implicit override val p: Parameters) extends ArtyShell {
+
+ //-----------------------------------------------------------------------
+ // Clock divider
+ //-----------------------------------------------------------------------
+ val slow_clock = Wire(Bool())
+
+ // Divide clock by 256, used to generate 32.768 kHz clock for AON block
+ withClockAndReset(clock_8MHz, ~mmcm_locked) {
+ val clockToggleReg = RegInit(false.B)
+ val (_, slowTick) = Counter(true.B, 256)
+ when (slowTick) {clockToggleReg := ~clockToggleReg}
+ slow_clock := clockToggleReg
+ }
+
+ //-----------------------------------------------------------------------
+ // DUT
+ //-----------------------------------------------------------------------
+
+ withClockAndReset(clock_32MHz, ck_rst) {
+ val dut = Module(new IC0ArtyDevKitPlatform)
+
+ //---------------------------------------------------------------------
+ // SPI flash IOBUFs
+ //---------------------------------------------------------------------
+
+ IOBUF(qspi_sck, dut.io.pins.qspi.sck)
+ IOBUF(qspi_cs, dut.io.pins.qspi.cs(0))
+
+ IOBUF(qspi_dq(0), dut.io.pins.qspi.dq(0))
+ IOBUF(qspi_dq(1), dut.io.pins.qspi.dq(1))
+ IOBUF(qspi_dq(2), dut.io.pins.qspi.dq(2))
+ IOBUF(qspi_dq(3), dut.io.pins.qspi.dq(3))
+
+ //---------------------------------------------------------------------
+ // JTAG IOBUFs
+ //---------------------------------------------------------------------
+
+ dut.io.pins.jtag.TCK.i.ival := IBUFG(IOBUF(jd_2).asClock).asUInt
+
+ IOBUF(jd_5, dut.io.pins.jtag.TMS)
+ PULLUP(jd_5)
+
+ IOBUF(jd_4, dut.io.pins.jtag.TDI)
+ PULLUP(jd_4)
+
+ IOBUF(jd_0, dut.io.pins.jtag.TDO)
+
+ // mimic putting a pullup on this line (part of reset vote)
+ SRST_n := IOBUF(jd_6)
+ PULLUP(jd_6)
+
+ // jtag reset
+ val jtag_power_on_reset = PowerOnResetFPGAOnly(clock_32MHz)
+ dut.io.jtag_reset := jtag_power_on_reset
+
+ // debug reset
+ dut_ndreset := dut.io.ndreset
+
+ //---------------------------------------------------------------------
+ // Assignment to package pins
+ //---------------------------------------------------------------------
+ // Pins IO0-IO13
+ //
+ // FTDI UART TX/RX are not connected to ck_io[0,1]
+ // the way they are on Arduino boards. We copy outgoing
+ // data to both places, switch 3 (sw[3]) determines whether
+ // input to UART comes from FTDI chip or gpio_16 (shield pin PD0)
+
+ val iobuf_ck0 = Module(new IOBUF())
+ iobuf_ck0.io.I := dut.io.pins.gpio.pins(16).o.oval
+ iobuf_ck0.io.T := ~dut.io.pins.gpio.pins(16).o.oe
+ attach(iobuf_ck0.io.IO, ck_io(0)) // UART0 RX
+
+ val iobuf_uart_txd = Module(new IOBUF())
+ iobuf_uart_txd.io.I := dut.io.pins.gpio.pins(16).o.oval
+ iobuf_uart_txd.io.T := ~dut.io.pins.gpio.pins(16).o.oe
+ attach(iobuf_uart_txd.io.IO, uart_txd_in)
+
+ // gpio(16) input is shared between FTDI TX pin and the Arduino shield pin using SW[3]
+ val sw_3_in = IOBUF(sw_3)
+ dut.io.pins.gpio.pins(16).i.ival := Mux(sw_3_in,
+ iobuf_ck0.io.O & dut.io.pins.gpio.pins(16).o.ie,
+ iobuf_uart_txd.io.O & dut.io.pins.gpio.pins(16).o.ie)
+
+ IOBUF(uart_rxd_out, dut.io.pins.gpio.pins(17))
+
+ // Shield header row 0: PD2-PD7
+ IOBUF(ck_io(2), dut.io.pins.gpio.pins(18))
+ IOBUF(ck_io(3), dut.io.pins.gpio.pins(19)) // PWM1(1)
+ IOBUF(ck_io(4), dut.io.pins.gpio.pins(20)) // PWM1(0)
+ IOBUF(ck_io(5), dut.io.pins.gpio.pins(21)) // PWM1(2)
+ IOBUF(ck_io(6), dut.io.pins.gpio.pins(22)) // PWM1(3)
+ IOBUF(ck_io(7), dut.io.pins.gpio.pins(23))
+
+ // Header row 1: PB0-PB5
+ IOBUF(ck_io(8), dut.io.pins.gpio.pins(0)) // PWM0(0)
+ IOBUF(ck_io(9), dut.io.pins.gpio.pins(1)) // PWM0(1)
+ IOBUF(ck_io(10), dut.io.pins.gpio.pins(2)) // SPI CS(0) / PWM0(2)
+ IOBUF(ck_io(11), dut.io.pins.gpio.pins(3)) // SPI MOSI / PWM0(3)
+ IOBUF(ck_io(12), dut.io.pins.gpio.pins(4)) // SPI MISO
+ IOBUF(ck_io(13), dut.io.pins.gpio.pins(5)) // SPI SCK
+
+ dut.io.pins.gpio.pins(6).i.ival := 0.U
+ dut.io.pins.gpio.pins(7).i.ival := 0.U
+ dut.io.pins.gpio.pins(8).i.ival := 0.U
+
+ // Header row 3: A0-A5 (we don't support using them as analog inputs)
+ // just treat them as regular digital GPIOs
+ IOBUF(ck_io(15), dut.io.pins.gpio.pins(9)) // A1 = CS(2)
+ IOBUF(ck_io(16), dut.io.pins.gpio.pins(10)) // A2 = CS(3) / PWM2(0)
+ IOBUF(ck_io(17), dut.io.pins.gpio.pins(11)) // A3 = PWM2(1)
+ IOBUF(ck_io(18), dut.io.pins.gpio.pins(12)) // A4 = PWM2(2) / SDA
+ IOBUF(ck_io(19), dut.io.pins.gpio.pins(13)) // A5 = PWM2(3) / SCL
+
+ // Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty
+ // assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active
+ IOBUF(led0_r, dut.io.pins.gpio.pins(1))
+ IOBUF(led0_g, dut.io.pins.gpio.pins(2))
+ IOBUF(led0_b, dut.io.pins.gpio.pins(3))
+
+ // Note that this is the one which is actually connected on the HiFive/Crazy88
+ // Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active
+ IOBUF(led1_r, dut.io.pins.gpio.pins(19))
+ IOBUF(led1_g, dut.io.pins.gpio.pins(21))
+ IOBUF(led1_b, dut.io.pins.gpio.pins(22))
+
+ // and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active
+ IOBUF(led2_r, dut.io.pins.gpio.pins(11))
+ IOBUF(led2_g, dut.io.pins.gpio.pins(12))
+ IOBUF(led2_b, dut.io.pins.gpio.pins(13))
+
+ // Only 19 out of 20 shield pins connected to GPIO pins
+ // Shield pin A5 (pin 14) left unconnected
+ // The buttons are connected to some extra GPIO pins not connected on the
+ // HiFive1 board
+ IOBUF(btn_0, dut.io.pins.gpio.pins(15))
+ IOBUF(btn_1, dut.io.pins.gpio.pins(30))
+ IOBUF(btn_2, dut.io.pins.gpio.pins(31))
+
+ val iobuf_btn_3 = Module(new IOBUF())
+ iobuf_btn_3.io.I := ~dut.io.pins.aon.pmu.dwakeup_n.o.oval
+ iobuf_btn_3.io.T := ~dut.io.pins.aon.pmu.dwakeup_n.o.oe
+ attach(btn_3, iobuf_btn_3.io.IO)
+ dut.io.pins.aon.pmu.dwakeup_n.i.ival := ~iobuf_btn_3.io.O & dut.io.pins.aon.pmu.dwakeup_n.o.ie
+
+ // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1
+ IOBUF(ja_0, dut.io.pins.gpio.pins(25)) // UART1 TX
+ IOBUF(ja_1, dut.io.pins.gpio.pins(24)) // UART1 RX
+
+ // SPI2 pins mapped to 6 pin ICSP connector (standard on later
+ // arduinos) These are connected to some extra GPIO pins not connected
+ // on the HiFive1 board
+ IOBUF(ck_ss, dut.io.pins.gpio.pins(26))
+ IOBUF(ck_mosi, dut.io.pins.gpio.pins(27))
+ IOBUF(ck_miso, dut.io.pins.gpio.pins(28))
+ IOBUF(ck_sck, dut.io.pins.gpio.pins(29))
+
+ // Use the LEDs for some more useful debugging things
+ IOBUF(led_0, ck_rst)
+ IOBUF(led_1, SRST_n)
+ IOBUF(led_2, dut.io.pins.aon.pmu.dwakeup_n.i.ival)
+ IOBUF(led_3, dut.io.pins.gpio.pins(14))
+
+ //---------------------------------------------------------------------
+ // Unconnected inputs
+ //---------------------------------------------------------------------
+
+ dut.io.pins.aon.erst_n.i.ival := ~reset_periph
+ dut.io.pins.aon.lfextclk.i.ival := slow_clock
+ dut.io.pins.aon.pmu.vddpaden.i.ival := 1.U
+ }
+}
--- /dev/null
+// See LICENSE for license details.
+package sifive.freedom.shakti.ic0artydevkit
+
+import Chisel._
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.coreplex._
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.util.ResetCatchAndSync
+import freechips.rocketchip.system._
+
+import sifive.blocks.devices.mockaon._
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.jtag._
+import sifive.blocks.devices.pwm._
+import sifive.blocks.devices.spi._
+import sifive.blocks.devices.uart._
+import sifive.blocks.devices.i2c._
+import sifive.blocks.devices.pinctrl._
+
+//-------------------------------------------------------------------------
+// PinGen
+//-------------------------------------------------------------------------
+
+object PinGen {
+ def apply(): BasePin = {
+ val pin = new BasePin()
+ pin
+ }
+}
+
+//-------------------------------------------------------------------------
+// IC0ArtyDevKitPlatformIO
+//-------------------------------------------------------------------------
+
+class IC0ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle {
+ val pins = new Bundle {
+ val jtag = new JTAGPins(() => PinGen(), false)
+ val gpio = new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))
+ val qspi = new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))
+ val aon = new MockAONWrapperPins()
+ }
+ val jtag_reset = Bool(INPUT)
+ val ndreset = Bool(OUTPUT)
+}
+
+//-------------------------------------------------------------------------
+// IC0ArtyDevKitPlatform
+//-------------------------------------------------------------------------
+
+class IC0ArtyDevKitPlatform(implicit val p: Parameters) extends Module {
+ val sys = Module(LazyModule(new IC0ArtyDevKitSystem).module)
+ val io = new IC0ArtyDevKitPlatformIO
+
+ // This needs to be de-asserted synchronously to the coreClk.
+ val async_corerst = sys.aon.rsts.corerst
+ // Add in debug-controlled reset.
+ sys.reset := ResetCatchAndSync(clock, async_corerst, 20)
+
+ //-----------------------------------------------------------------------
+ // Check for unsupported rocket-chip connections
+ //-----------------------------------------------------------------------
+
+ require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported");
+
+ //-----------------------------------------------------------------------
+ // Build GPIO Pin Mux
+ //-----------------------------------------------------------------------
+ // Pin Mux for UART, SPI, PWM
+ // First convert the System outputs into "IOF" using the respective *GPIOPort
+ // converters.
+
+ val sys_uart = sys.uart
+ val sys_pwm = sys.pwm
+ val sys_spi = sys.spi
+ val sys_i2c = sys.i2c
+
+ val uart_pins = sys.outer.uartParams.map { c => Wire(new UARTPins(() => PinGen()))}
+ val pwm_pins = sys.outer.pwmParams.map { c => Wire(new PWMPins(() => PinGen(), c))}
+ val spi_pins = sys.outer.spiParams.map { c => Wire(new SPIPins(() => PinGen(), c))}
+ val i2c_pins = sys.outer.i2cParams.map { c => Wire(new I2CPins(() => PinGen()))}
+
+ (uart_pins zip sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)}
+ (pwm_pins zip sys_pwm) map {case (p, r) => PWMPinsFromPort(p, r) }
+ (spi_pins zip sys_spi) map {case (p, r) => SPIPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)}
+ (i2c_pins zip sys_i2c) map {case (p, r) => I2CPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)}
+
+ //-----------------------------------------------------------------------
+ // Default Pin connections before attaching pinmux
+
+ for (iof_0 <- sys.gpio(0).iof_0.get) {
+ iof_0.default()
+ }
+
+ for (iof_1 <- sys.gpio(0).iof_1.get) {
+ iof_1.default()
+ }
+
+ //-----------------------------------------------------------------------
+
+ val iof_0 = sys.gpio(0).iof_0.get
+ val iof_1 = sys.gpio(0).iof_1.get
+
+ // SPI1 (0 is the dedicated)
+ BasePinToIOF(spi_pins(0).cs(0), iof_0(2))
+ BasePinToIOF(spi_pins(0).dq(0), iof_0(3))
+ BasePinToIOF(spi_pins(0).dq(1), iof_0(4))
+ BasePinToIOF(spi_pins(0).sck, iof_0(5))
+ BasePinToIOF(spi_pins(0).dq(2), iof_0(6))
+ BasePinToIOF(spi_pins(0).dq(3), iof_0(7))
+ BasePinToIOF(spi_pins(0).cs(1), iof_0(8))
+ BasePinToIOF(spi_pins(0).cs(2), iof_0(9))
+ BasePinToIOF(spi_pins(0).cs(3), iof_0(10))
+
+ // SPI2
+ BasePinToIOF(spi_pins(1).cs(0), iof_0(26))
+ BasePinToIOF(spi_pins(1).dq(0), iof_0(27))
+ BasePinToIOF(spi_pins(1).dq(1), iof_0(28))
+ BasePinToIOF(spi_pins(1).sck, iof_0(29))
+ BasePinToIOF(spi_pins(1).dq(2), iof_0(30))
+ BasePinToIOF(spi_pins(1).dq(3), iof_0(31))
+
+ // I2C
+ if (sys.outer.i2cParams.length == 1) {
+ BasePinToIOF(i2c_pins(0).sda, iof_0(12))
+ BasePinToIOF(i2c_pins(0).scl, iof_0(13))
+ }
+
+ // UART0
+ BasePinToIOF(uart_pins(0).rxd, iof_0(16))
+ BasePinToIOF(uart_pins(0).txd, iof_0(17))
+
+ // UART1
+ BasePinToIOF(uart_pins(1).rxd, iof_0(24))
+ BasePinToIOF(uart_pins(1).txd, iof_0(25))
+
+ //PWM
+ BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) )
+ BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) )
+ BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) )
+ BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) )
+
+ BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19))
+ BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20))
+ BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21))
+ BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22))
+
+ BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10))
+ BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11))
+ BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12))
+ BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13))
+
+ //-----------------------------------------------------------------------
+ // Drive actual Pads
+ //-----------------------------------------------------------------------
+
+ // Result of Pin Mux
+ GPIOPinsFromPort(io.pins.gpio, sys.gpio(0))
+
+ // Dedicated SPI Pads
+ SPIPinsFromPort(io.pins.qspi, sys.qspi(0), clock = sys.clock, reset = sys.reset, syncStages = 3)
+
+ // JTAG Debug Interface
+ val sjtag = sys.debug.systemjtag.get
+ JTAGPinsFromPort(io.pins.jtag, sjtag.jtag)
+ sjtag.reset := io.jtag_reset
+ sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
+
+ io.ndreset := sys.debug.ndreset
+
+ // AON Pads -- direct connection is OK because
+ // EnhancedPin is hard-coded in MockAONPads
+ // and thus there is no .fromPort method.
+ io.pins.aon <> sys.aon.pins
+}
--- /dev/null
+// See LICENSE for license details.
+package sifive.freedom.shakti.ic0artydevkit
+
+import Chisel._
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.coreplex._
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.system._
+
+import sifive.blocks.devices.mockaon._
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.pwm._
+import sifive.blocks.devices.spi._
+import sifive.blocks.devices.uart._
+import sifive.blocks.devices.i2c._
+
+//-------------------------------------------------------------------------
+// IC0ArtyDevKitSystem
+//-------------------------------------------------------------------------
+
+class IC0ArtyDevKitSystem(implicit p: Parameters) extends RocketCoreplex
+ with HasPeripheryMaskROMSlave
+ with HasPeripheryDebug
+ with HasPeripheryMockAON
+ with HasPeripheryUART
+ with HasPeripherySPIFlash
+ with HasPeripherySPI
+ with HasPeripheryGPIO
+ with HasPeripheryPWM
+ with HasPeripheryI2C {
+ override lazy val module = new IC0ArtyDevKitSystemModule(this)
+}
+
+class IC0ArtyDevKitSystemModule[+L <: IC0ArtyDevKitSystem](_outer: L)
+ extends RocketCoreplexModule(_outer)
+ with HasPeripheryDebugModuleImp
+ with HasPeripheryUARTModuleImp
+ with HasPeripherySPIModuleImp
+ with HasPeripheryGPIOModuleImp
+ with HasPeripherySPIFlashModuleImp
+ with HasPeripheryMockAONModuleImp
+ with HasPeripheryPWMModuleImp
+ with HasPeripheryI2CModuleImp {
+ // Reset vector is set to the location of the mask rom
+ val maskROMParams = p(PeripheryMaskROMKey)
+ global_reset_vector := maskROMParams(0).address.U
+}
projects / freedom-sifive.git / commitdiff