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Add variable to control what program gets flashed to FPGA.
[freedom-sifive.git] / fpga / e300artydevkit / script / prologue.tcl
2016-12-01 Richard XiaMerge pull request #6 from sifive/remove-consts-vh blob | commitdiff | raw
2016-11-30 Richard XiaRemove verilog header files built from Chisel .prm... blob | commitdiff | raw
2016-11-29 SiFiveInitial commit. blob | commitdiff | raw | diff to current
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