Remove verilog header files built from Chisel .prm file.
[freedom-sifive.git] / fpga / e300artydevkit /
drwxr-xr-x   ..
-rw-r--r-- 73 .gitignore
-rw-r--r-- 594 Makefile
drwxr-xr-x - constrs
drwxr-xr-x - script
drwxr-xr-x - src