tests: arch-power: Add 64-bit hello binaries This adds 64-bit statically linked big and little endian binaries for the hello test program. It should be noted that all possible combinations of ABI version and endianness are possible for 64-bit binaries. However, standard toolchains always use ELF ABI v1 for big endian and ELF ABI v2 for little endian binaries. Change-Id: I2dca7eaa2b04a7b68b117ada799d4c3bb69368be Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
tests: arch-power: Move 32-bit hello binary This moves the 32-bit hello binary for Power under the linux subdirectory like it was originally before being removed and reintroduced. Change-Id: I5f3da38f9abdda90b31755ce7e7c955838cc7289 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
tests: arch-power: Add support for building hello Commit a440108cc ("tests: Add Makefiles for hello") introduced Makefiles for building the hello test binary for ARM and x86 using dockcross. Since dockcross also provides an image with a 64-bit little endian toolchain for Power, this adds a Makefile for building the hello binary. As of this moment, 64-bit little endian (ppc64le) is the prevalent variant supported by most distributions. Hence, we are currently limited to only building the binary for this variant. Change-Id: Ic20322ca33c69634d9f17d30b29e522cc35742fb Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
arch-power: Update copyrights Change-Id: Ifabd1e7178b5250767a2b560b57570512b732278 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
arch-power: Fix load-store instructions for timing cpu To properly implement load-store instructions for use with the TimingSimpleCPU model, the initiateAcc() part of the instruction should only be responsible for performing the effective address computation and then initiating memory access. The completeAcc() part of the instruction should then be responsible for setting the condition register flags or updating the base register based on the outcome of the memory access. This fixes the following instructions: * Load Byte and Zero with Update (lbzu) * Load Halfword and Zero with Update (lhzu) * Load Halfword Algebraic with Update (lhau) * Load Word and Zero with Update (lwzu) * Load Doubleword with Update (ldu) * Load Floating Single with Update (lfsu) * Load Floating Double with Update (lfdu) * Load Byte and Zero with Update Indexed (lbzux) * Load Halfword and Zero with Update Indexed (lhzux) * Load Halfword Algebraic with Update Indexed (lhaux) * Load Word and Zero with Update Indexed (lwzux) * Load Word Algebraic with Update Indexed (lwaux) * Load Doubleword with Update Indexed (ldux) * Load Floating Single with Update Indexed (lfsux) * Load Floating Double with Update Indexed (lfdux) * Load Byte And Reserve Indexed (lbarx) * Load Halfword And Reserve Indexed (lharx) * Load Word And Reserve Indexed (lwarx) * Load Doubleword And Reserve Indexed (ldarx) * Store Byte with Update (stbu) * Store Halfword with Update (sthu) * Store Word with Update (stwu) * Store Doubleword with Update (stdu) * Store Byte with Update Indexed (stbux) * Store Halfword with Update Indexed (sthux) * Store Word with Update Indexed (stwux) * Store Doubleword with Update Indexed (stdux) * Store Byte Conditional Indexed (stbcx.) * Store Halfword Conditional Indexed (sthcx.) * Store Word Conditional Indexed (stwcx.) * Store Doubleword Conditional Indexed (stdcx.) * Store Floating Single with Update (stfsu) * Store Floating Double with Update (stdsu) * Store Floating Single with Update Indexed (stfsux) * Store Floating Double with Update Indexed (stfdux) Change-Id: If5f720619ec3c40a90c1362a9dfc8cc204e57acf Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
arch-power: Add multi-mode debugging support This adds multi-mode support for remote debugging via GDB with the addition of the XML target description files for both 32-bit and 64-bit variants of the Power architecture. Proper byte order conversions have also been added. Since, MSR has now been modeled to some extent, it is also exposed by getRegs() but setRegs() does not modify it. Similarly, the target descriptions require FPSCR to also be part of the payload and hence, it has been added too. Change-Id: I156fdccb791f161959dbb2c3dd8ab1e510d9cd4b Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
arch-power: Fix process initialization During process initialization, special purpose registers, represented as misc registers, should either be explicitly set or cleared. These contain flag bits which might have unforseen side effects on the execution of a program. Change-Id: If7c5af9a93283a53717cc8cbba4bf373a7e40560 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
arch-power: Add multi-mode support This adds multi-mode support and allows the simulator to read, interpret and execute 32bit and 64-bit, big and little endian binaries in syscall emulation mode. During process initialization, a minimal set of hardware capabilities are also advertised by the simulator to show support for 64-bit mode and little endian byte order. This also adds some fixups specific to 64-bit ELF ABI v1 that readjust the entry point and symbol table due to the use of function descriptors. Change-Id: I124339eff7b70dbd14e50ff970340c88c13bd0ad Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
arch-power: Add MSR and associated dependencies This adds the definition of the Machine State Register (MSR) in preparation for multi-mode support. The MSR has bits that define the state of the processor. This defines all the bitfields and sets the ones that are typically used for userspace environments. In preparation for multi-mode support, the SF and LE bits are used by instructions to check if the simulation is running in 64-bit mode and if memory accesses are to be performed in little endian byte order respectively. This introduces changes in areas such as target address computation for branch instructions, carry and overflow computation for arithmetic instructions, etc. Change-Id: If9ac69415ca85b0c873bd8579e7d1bd2219eac62 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
arch-power: Add hardware features This adds definitions for the hardware feature bits that are currently available from the AT_HWCAP and AT_HWCAP2 auxv entries for the Power architecture. These are being defined for future use. Change-Id: I8214a4a26c502b1b0f31837069084b2e7cb31c51 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
arch-power: Refactor process initialization This generalizes parts of the process initialization routines in preparation for multi-mode support and adds flexibility in terms of data types and byte order used for setting up the environment corresponding to the mode in use. Change-Id: Ia9efb93d044682af8b0f0809bca64a17570bf197 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
arch-power: Add byte order attribute for PC state This adds byte order as an attribute for PC state by introducing a new PCState class. The decoder can now fetch instructions bytes in the specified byte order in preparation for multi-mode support. Change-Id: I917333df88114a733cc5a8077cc420d5328f608b Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
base: Add byte order attribute for object files This adds byte order as an attribute for object files by introducing new members to the ObjectFile class. This is populated by the looking at the ELF headers. Change-Id: Ibe55699175cc0295e0c9d49bdbe02e580988bc4f Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
arch-power: Refactor argument registers This reintroduces the argument register constants that were removed in commit 7bb456f02 ("arch-power: Delete unused register related constants"), adds a definition for the sixth argument register and switches to these constants to specify the arguments used by the system call ABI. Change-Id: I5804f4d2b27a04d0e7b69132e5abce5761b239f5 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
arch-power: Add time base instructions This models a pseudo time base using the simulator ticks and adds the following instructions. * Move From Time Base (mftb) * Move From Time Base Upper (mftbu) Change-Id: Idb619ec3179b2a85925998282075bde8651c68c2 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
arch-power: Add move condition field instructions This adds the following instructions. * Move to CR from XER Extended (mcrxrx) * Move To One Condition Register Field (mtocrf) * Move From One Condition Register Field (mfocrf) Change-Id: I5014160d77b1b759c1cb8cba34e6dd20eb2b5205 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
arch-power: Fix move condition field instructions This introduces the S field for X form instructions which is used to specify signed versus unsigned comparison. The Power ISA does not specify a formal name for the third 1-bit opcode field required for decoding XFX form move to and from CR field instructions, the S field can be used to achieve the same as it has the same span and position. This fixes the following instructions. * Move To Condition Register Fields (mtcrf) * Move From Condition Register (mfcr) Change-Id: I8d291f707cd063781f0497f7226bebfc47bd9e63 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
arch-power: Add trap instructions This introduces new classes and new formats for D and X form instructions, the TO field that is used to encode the trap conditions and adds the following instructions. * Trap Word Immediate (twi) * Trap Word (tw) * Trap Doubleword Immediate (tdi) * Trap Doubleword (td) Change-Id: I029147ef643c2ee6794426e5e90af4d75f22e92e Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
arch-power: Add doubleword rotate instructions This introduces a new class and a new format for MD and MDS form instructions where the shift amount, mask begin and mask end are specified by two fields that must be concatenated and adds the following instructions. * Rotate Left Doubleword Immediate then Clear Left (rldicl[.]) * Rotate Left Doubleword Immediate then Clear Right (rldicr[.]) * Rotate Left Doubleword Immediate then Clear (rldic[.]) * Rotate Left Doubleword then Clear Left (rldcl[.]) * Rotate Left Doubleword then Clear Right (rldcr[.]) * Rotate Left Doubleword Immediate then Mask Insert (rldimi[.]) Change-Id: Id7f1f24032242ccfdfda2f1aefd6fe9f0331f610 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
arch-power: Add fields for MD and MDS form instructions This introduces the extended opcode fields for MD and MDS form instructions and the mb and me fields which are concatenated with the MB and ME fields respectively for specifying mask bounds for doubleword operands. Change-Id: I2c3366794ed42f5d31ba1d69e360c0ac67c74e06 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>