RELEASE-NOTES.md

   1 # Version 20.0.0.3
   2
   3 **[HOTFIX]** When using the ARM ISA, gem5 could crash when a guest tried to call m5ops. This was due to `m5ops_base` being incorrectly declared in `src/arch/arm/ArmSystem.py`. A fix was applied to remove this declaration.
   4
   5 # Version 20.0.0.2
   6
   7 **[HOTFIX]** A patch was applied to fix the RubyPrefetcher with MESI_Three_Level. Prior to this fix a segfault occurred.
   8
   9 # Version 20.0.0.1
  10
  11 **[HOTFIX]** A fix was applied to stop incorrect clock frequences being reported due to rounding errors.
  12
  13 # Version 20.0.0.0
  14
  15 Welcome to our first "official" gem5 release!
  16 gem5 v19.0.0.0 was a "test" release, but this one has release notes, so it must be official!
  17
  18 Thank you to everyone that made this release possible!
  19 This has been a very productive release with over [70 issues closed](https://gem5.atlassian.net/), over 500 commits, and 31 unique contributors.
  20 Below are some of the highlights, though I'm sure I've missed some important changes.
  21
  22 ## New features
  23
  24 * [gem5-resources repository](https://gem5.googlesource.com/public/gem5-resources/)
  25   * This new repository will store all of the *sources* (e.g., code) used to create testing and research resources. This includes disk images, testing binaries, kernel binaries, etc.
  26   * Binaries created with the sources are hosted on dist.gem5.org.
  27   * Details on the new page for resources: <http://www.gem5.org/documentation/general_docs/gem5_resources>.
  28 * Memory SimObjects can now be initialized using an image file using the image_file parameter.
  29 * **[USER-FACING CHANGE]** The m5 utility has been revamped with a new build system based on scons, tests, and updated and more consistent feature support.
  30   * To build, now use `scons build/<arch>/out/m5`, not `make`.
  31   * [Documentation](http://www.gem5.org/documentation/general_docs/m5ops/) coming soon.
  32 * Robust support for marshalling data from a function call inside the simulation to a function within gem5 using a predefined set of rules.
  33   * Developers can specify an ABI for guest<->simulator calls and then "just call functions".
  34   * Unifies pseudo-inst, syscall, and other support.
  35   * Code within gem5 has been updated. However, users which added new pseudo-ops may have to update their code.
  36 * **[PYTHON API CHANGE]** Workload configuration pulled out into its own object, simplifying the System object and making workload configuration more modular and flexible.
  37   * All full system config/run scripts must be updated (e.g., anything that used the `LinuxX86System` or similar SimObject).
  38   * Many of the parameters of `System` are now parameters of the `Workload` (see `src/sim/Workload.py`).
  39     * For instance, many parameters of `LinuxX86System` are now part of `X86FsLinux` which is now the `workload` parameter of the `System` SimObject.
  40   * See https://gem5-review.googlesource.com/c/public/gem5/+/24283/ and https://gem5-review.googlesource.com/c/public/gem5/+/26466 for more details.
  41 * Sv39 paging has been added to the RISC-V ISA, bringing gem5 close to running Linux on RISC-V.
  42   * (Some) Baremetal OSes are now supported.
  43 * Improvements to DRAM model:
  44   * Added support for verifying available command bandwidth.
  45   * Added support for multi-cycle commands.
  46   * Added new timing parameters.
  47   * Added ability to interleave bursts.
  48   * Added LPDDR5 configurations.
  49 * **[Developer change]** We are beginning to document gem5 APIs.
  50   * Currently, only SimObjects and the APIs they depend on have been documented.
  51   * We are using doxygen to mark "stable APIs" and will use manual code review to make sure the APIs stay stable.
  52   * More information will be coming during gem5-20.1 development.
  53
  54 ## Removed features
  55
  56 * Support for the ALPHA ISA has been dropped.
  57   * All ALPHA ISA code has been removed
  58   * Old "rcS" scripts for ALPHA have been removed
  59
  60 ## New supported platforms
  61
  62 * Compiling and running gem5 with Python 3 is now fully supported.
  63   * Lots of code changes required for this.
  64   * There may still be some python code that's not up to date. Please open a [Jira ticket](https://gem5.atlassian.net/) if you find any code that doesn't work with python3.
  65 * gem5 now supports Ubuntu 20.04.
  66 * Compiling gem5 with GCC 8 and 9 is now supported.
  67 * Compiling with clang up to version 9 is now supported.
  68
  69 ## Testing improvements
  70
  71 * Scons-based tests have been migrated to the testlib framework.
  72   * Tests can now be run with `tests/main.py`, except for the unittests.
  73   * Please consult TESTING.md for more information on how these may be run.
  74 * We are continuing to work on CI tests. Most of the plumbing is there for Google Cloud Build integration. See [the Jira issue](https://gem5.atlassian.net/browse/GEM5-237) for details.
  75
  76 ## Other API changes
  77
  78 * **[API CHANGE]** Ruby's prefetcher renamed to RubyPrefetcher.
  79   * Any SLICC protocols with prefetchers need to be updated.
  80   * Some config scripts for Ruby protocols with prefetchers may need to be updated.
  81 * **[API CHANGE]** SE mode improvements.
  82   * Better support for the mmap and related syscalls.
  83   * A new virtual memory area API for tracking SE mode allocations.
  84   * When implementing syscalls, the way that guest memory is allocated changes. All code in gem5 is updated, but if there are any external syscalls, they may need be updated.
  85 * **[COMMAND LINE CHANGE]** The `--disk-image` argument to `fs.py` is now optional.
  86   * However, the disk image names *are no longer implied*.
  87   * The script still implicitly searches `M5_PATH`, but the name of the disk image must be specified.
  88 * **[API CHANGE]** SLICC `queueMemory` is now `enqueue`.
  89   * All protocol configs must be updated with another message buffer in the memory controllers (directories).
  90   * All protocol SLICC files must replace `queueMemoryRead` and `queueMemoryWrite` with `enqueue` to another "special" message buffer named `memQueue`.
  91   * This allows finite buffering between the cache controllers and DRAMCtrl.
  92 * **[API CHANGE]** Added Prefetcher namespace
  93   * All prefetchers' names have changed from `*Prefetcher` to `Prefetcher::*`
  94   * If you have any prefetchers that are not in the gem5 mainline, your code will likely need to be updated.
  95
  96 ## Other changes
  97
  98 * Implemented ARMv8.3-CompNum, SIMD complex number extension.
  99 * Support for Arm Trusted Firmware + u-boot with the new VExpress_GEM5_Foundation platform
 100 * Removed author list from source files.
 101   * This was originally so future people would know who to contact.
 102   * However, it was difficult to maintain and quickly out of date.
 103   * Copyright is unchanged.
 104 * Improvements to gem5's power model.
 105 * MESI_Three_Level Ruby protocol bugfixes.
 106 * Ruby functional reads now work in more cases.
 107 * Indirect branch stats work correctly now.