Merge ARM into the head. ARM will compile but may not actually work.

[gem5.git] / src / arch / arm / ArmTLB.py

diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index 21253edef032579ce7254aa5b3d3dd4e2f3456b3..fa9faaddf8fa83762c922ae3a8666e6f6a67881c 100644 (file)
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -34,25 +34,21 @@ from m5.params import *
 class ArmTLB(SimObject):
     abstract = True
     type = 'ArmTLB'
-    cxx_namespace = 'ArmISA'
-    cxx_class = 'TLB'
+    cxx_class = 'ArmISA::TLB'
     size = Param.Int("TLB size")
 
 class ArmDTB(ArmTLB):
     type = 'ArmDTB'
-    cxx_namespace = 'ArmISA'
-    cxx_class = 'DTB'
+    cxx_class = 'ArmISA::DTB'
     size = 64
 
 class ArmITB(ArmTLB):
     type = 'ArmITB'
-    cxx_namespace = 'ArmISA'
-    cxx_class = 'ITB'
+    cxx_class = 'ArmISA::ITB'
     size = 64
 
 class ArmUTB(ArmTLB):
     type = 'ArmUTB'
-    cxx_namespace = 'ArmISA'
-    cxx_class = 'UTB'
+    cxx_class = 'ArmISA::UTB'
     size = 64