arch-power: Add trap instructions

[gem5.git] / src / arch / power / insts / integer.cc

diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc
index 0631749e2e9bcfebb63168b864e0b66678fda866..115b8674fa041995c35554d90c443bbdb25244b9 100644 (file)
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -878,3 +878,103 @@ IntConcatRotateOp::generateDisassembly(
 
     return ss.str();
 }
+
+
+std::string
+IntTrapOp::generateDisassembly(
+        Addr pc, const Loader::SymbolTable *symtab) const
+{
+    std::string ext;
+    std::stringstream ss;
+    bool printSrcs = true;
+    bool printCond = false;
+
+    // Generate the correct mnemonic
+    std::string myMnemonic(mnemonic);
+
+    // Special cases
+    if (!myMnemonic.compare("tw") &&
+        (srcRegIdx(0).index() == 0) && (srcRegIdx(1).index() == 0)) {
+        myMnemonic = "trap";
+        printSrcs = false;
+    } else {
+        ext = suffix();
+        if (!ext.empty() &&
+            (!myMnemonic.compare("tw") || !myMnemonic.compare("td"))) {
+            myMnemonic += ext;
+        } else {
+            printCond = true;
+        }
+    }
+
+    ccprintf(ss, "%-10s ", myMnemonic);
+
+    // Print the trap condition
+    if (printCond) {
+        ss << unsigned(tcond);
+    }
+
+    // Print the source registers
+    if (printSrcs) {
+        if (_numSrcRegs > 0) {
+            if (printCond) {
+                ss << ", ";
+            }
+            printReg(ss, srcRegIdx(0));
+        }
+
+        if (_numSrcRegs > 1) {
+            ss << ", ";
+            printReg(ss, srcRegIdx(1));
+        }
+    }
+
+    return ss.str();
+}
+
+
+std::string
+IntImmTrapOp::generateDisassembly(
+        Addr pc, const Loader::SymbolTable *symtab) const
+{
+    std::string ext;
+    std::stringstream ss;
+    bool printCond = false;
+
+    // Generate the correct mnemonic
+    std::string myMnemonic(mnemonic);
+
+    // Special cases
+    ext = suffix();
+    if (!ext.empty()) {
+        if (!myMnemonic.compare("twi")) {
+            myMnemonic = "tw" + ext + "i";
+        } else if (!myMnemonic.compare("tdi")) {
+            myMnemonic = "td" + ext + "i";
+        } else {
+            printCond = true;
+        }
+    } else {
+        printCond = true;
+    }
+
+    ccprintf(ss, "%-10s ", myMnemonic);
+
+    // Print the trap condition
+    if (printCond) {
+        ss << unsigned(tcond);
+    }
+
+    // Print the source registers
+    if (_numSrcRegs > 0) {
+        if (printCond) {
+            ss << ", ";
+        }
+        printReg(ss, srcRegIdx(0));
+    }
+
+    // Print the immediate value
+    ss << ", " << simm;
+
+    return ss.str();
+}