arch-power: Fix load-store instructions for timing cpu

[gem5.git] / src / arch / power / isa / decoder.isa

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index aeee29a034289071de4841612ac52a78b2f79d17..1db81599b9d6ffc75455b9db6964ac103b3b8450 100644 (file)
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -313,17 +313,21 @@ decode PO default Unknown::unknown() {
         // Ra and Rb are source registers, Rt is the destintation.
         format LoadIndexOp {
             87: lbzx({{ Rt = Mem_ub; }});
-            52: lbarx({{ Rt = Mem_ub; Rsv = 1; RsvLen = 1; RsvAddr = EA; }});
+            52: lbarx({{ Rt = Mem_ub; }},
+                      {{ Rsv = 1; RsvLen = 1; RsvAddr = EA; }});
             279: lhzx({{ Rt = Mem_uh; }});
             343: lhax({{ Rt = Mem_sh; }});
-            116: lharx({{ Rt = Mem_uh; Rsv = 1; RsvLen = 2; RsvAddr = EA; }});
+            116: lharx({{ Rt = Mem_uh;}},
+                       {{  Rsv = 1; RsvLen = 2; RsvAddr = EA; }});
             790: lhbrx({{ Rt = swap_byte(Mem_uh); }});
             23: lwzx({{ Rt = Mem_uw; }});
             341: lwax({{ Rt = Mem_sw; }});
-            20: lwarx({{ Rt = Mem_uw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
+            20: lwarx({{ Rt = Mem_uw; }},
+                      {{ Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
             534: lwbrx({{ Rt = swap_byte(Mem_uw); }});
             21: ldx({{ Rt = Mem; }});
-            84: ldarx({{ Rt = Mem_ud; Rsv = 1; RsvLen = 8; RsvAddr = EA; }});
+            84: ldarx({{ Rt = Mem_ud; }},
+                      {{ Rsv = 1; RsvLen = 8; RsvAddr = EA; }});
             532: ldbrx({{ Rt = swap_byte(Mem); }});
             535: lfsx({{ Ft_sf = Mem_sf; }});
             599: lfdx({{ Ft = Mem_df; }});
@@ -344,8 +348,9 @@ decode PO default Unknown::unknown() {
         format StoreIndexOp {
             215: stbx({{ Mem_ub = Rs_ub; }});
             694: stbcx({{
-                bool store_performed = false;
                 Mem_ub = Rs_ub;
+            }}, {{
+                bool store_performed = false;
                 if (Rsv) {
                     if (RsvLen == 1) {
                         if (RsvAddr == EA) {
@@ -361,8 +366,9 @@ decode PO default Unknown::unknown() {
             }});
             407: sthx({{ Mem_uh = Rs_uh; }});
             726: sthcx({{
-                bool store_performed = false;
                 Mem_uh = Rs_uh;
+            }}, {{
+                bool store_performed = false;
                 if (Rsv) {
                     if (RsvLen == 2) {
                         if (RsvAddr == EA) {
@@ -379,8 +385,9 @@ decode PO default Unknown::unknown() {
             918: sthbrx({{ Mem_uh = swap_byte(Rs_uh); }});
             151: stwx({{ Mem_uw = Rs_uw; }});
             150: stwcx({{
-                bool store_performed = false;
                 Mem_uw = Rs_uw;
+            }}, {{
+                bool store_performed = false;
                 if (Rsv) {
                     if (RsvLen == 4) {
                         if (RsvAddr == EA) {
@@ -397,8 +404,9 @@ decode PO default Unknown::unknown() {
             662: stwbrx({{ Mem_uw = swap_byte(Rs_uw); }});
             149: stdx({{ Mem = Rs }});
             214: stdcx({{
-                bool store_performed = false;
                 Mem = Rs;
+            }}, {{
+                bool store_performed = false;
                 if (Rsv) {
                     if (RsvLen == 8) {
                         if (RsvAddr == EA) {