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(parent: a4bd492) | patch
cpu,configs: let RISC-V use the PT walker cache.
authorNils Asmussen <nils.asmussen@barkhauseninstitut.org>
Sat, 21 Mar 2020 10:01:31 +0000 (11:01 +0100)
committerNils Asmussen <nils.asmussen@barkhauseninstitut.org>
Wed, 29 Apr 2020 11:41:55 +0000 (11:41 +0000)
commit2403018690e8eda5c7b71c9f50416cf0a0840d67
treecd8a05805fd390342d3e87a6c5719e20b228b708tree
parenta4bd49215827b78e276e6ba4f2718c17a349caa8commit | diff
cpu,configs: let RISC-V use the PT walker cache.

Change-Id: I19b1dd9e3c55c433c897988d36e6715017273c66
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26988
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
configs/common/CacheConfig.py diff | blob | history
configs/common/Caches.py diff | blob | history
src/cpu/BaseCPU.py diff | blob | history