arch-x86: Make JRCXZ instruction do 64-bit jump
authorKyle Roarty <kyleroarty1716@gmail.com>
Sun, 31 Jan 2021 01:45:14 +0000 (19:45 -0600)
committerMatt Sinclair <mattdsinclair@gmail.com>
Thu, 4 Feb 2021 00:06:59 +0000 (00:06 +0000)
commit4060208a0415f55ccfd1e9592bfdfc757cbd8704
tree960b031648238e5d764661f061786edddbea9a43
parent7753a02663edcd1a7751c5f955881edb49b4a158
arch-x86: Make JRCXZ instruction do 64-bit jump

Per the AMD64 Architecture Programming Manual:

The size of the count register (CX, ECX, or RCX) depends on the
address-size attribute of the JrCXZ instruction. Therefore, JRCXZ can
only be executed in 64-bit mode

and

In 64-bit mode, the operand size defaults to 64 bits. The processor
sign-extends the 8-bit displacement value to 64 bits before adding it
to the RIP.

This patch also renames the instruction from JRCX to JRCXZ to match the
language in the programming manual.

Change-Id: Id55147d0602ff41ad6aaef483bef722ff56cae62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40195
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/x86/isa/decoder/one_byte_opcodes.isa
src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py