configs: add option for memory channel intlv.
authorAdrian Herrera <adrian.herrera@arm.com>
Mon, 6 Apr 2020 12:53:03 +0000 (13:53 +0100)
committerAdrian Herrera <adrian.herrera@arm.com>
Thu, 9 Apr 2020 08:00:36 +0000 (08:00 +0000)
commit4cde1075d6c0d327a64b6a09216a6b9e964620ed
treea9c6fdd9520ee71b66d7a3e29f46bc162ed5bb3f
parent049aaf41f54be4ed6c612d1d1ac865508a67e691
configs: add option for memory channel intlv.

Current memory channel interleave is hard-coded to be maximum between 128
and system's cache line size. Making this value configurable enables use
cases with DMA masters accessing at higher than 128 block granularity.

Change-Id: I8123fa307efd3fd8f16c815ee74a84844bb51edb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27629
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
configs/common/MemConfig.py
configs/common/Options.py