arch-arm: Implement ARM8.1-VHE feature
authorJordi Vaquero <jordi.vaquero@metempsy.com>
Sat, 20 Jun 2020 12:22:03 +0000 (14:22 +0200)
committerJordi Vaquero <jordi.vaquero@metempsy.com>
Mon, 27 Jul 2020 17:23:55 +0000 (17:23 +0000)
commit980888eb81635dbca40b11fe557be3fb1da37573
treed10fda99aea044a3839e63c346da073fa88590eb
parent4b58a1d915bbca315203b8ed2296604b7781f8a6
arch-arm: Implement ARM8.1-VHE feature

This commit implemented the VHE feature in ARMv8. This consist in 3
parts
    1. Register decl/init and register redirection from el1 to el2
        miscregs.cc/hh
        miscregs_types.hh
        isa.cc
        utility.cc/hh
    2. Definition of new EL2&0 translation regime.
        tlb.cc/hh
        table_walker.cc
        pagetable.hh
        tlbi_op.hh
        isa.cc ( for tlb invalidation functions)
    3. Self Debug adaptation for VHE
        self_debug.cc
    4. Effects on AMO/IMO/FMO interruptions
        faults.cc
        interrupts.hh

JIRA: https://gem5.atlassian.net/browse/GEM5-682

Change-Id: I478389322c295b1ec560571071626373a8c2af61
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31177
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
20 files changed:
src/arch/arm/ArmISA.py
src/arch/arm/insts/misc64.cc
src/arch/arm/insts/static_inst.cc
src/arch/arm/interrupts.hh
src/arch/arm/isa.cc
src/arch/arm/isa.hh
src/arch/arm/isa/insts/ldr64.isa
src/arch/arm/isa/insts/str64.isa
src/arch/arm/miscregs.cc
src/arch/arm/miscregs.hh
src/arch/arm/miscregs_types.hh
src/arch/arm/pagetable.hh
src/arch/arm/self_debug.cc
src/arch/arm/self_debug.hh
src/arch/arm/table_walker.cc
src/arch/arm/tlb.cc
src/arch/arm/tlb.hh
src/arch/arm/tlbi_op.cc
src/arch/arm/utility.cc
src/arch/arm/utility.hh