arch,cpu: Move a Decode DPRINTF into the arch Decoder classes.
authorGabe Black <gabe.black@gmail.com>
Fri, 29 Jan 2021 01:34:43 +0000 (17:34 -0800)
committerGabe Black <gabe.black@gmail.com>
Fri, 5 Feb 2021 03:06:00 +0000 (03:06 +0000)
commitb3254e142fd32c56a4f31a95ad81d1366ad13011
tree01ebf38c6b90e13d8516ed29cd6bd72faffca04c
parent344ea0330a9efa0c2d9656ee4dedf4ec2fcda2cb
arch,cpu: Move a Decode DPRINTF into the arch Decoder classes.

This DPRINTF accesses the ExtMachInst typed machInst member of the
StaticInst class, and so is ISA dependent. Move the DPRINTF to where the
instructions are actually decoded where that type doesn't have to be
disambiguated.

Also, this change makes this DPRINTF more accurate, since microops are
not really "decoded" when they are extracted from a macroop. The process
of unpacking them to feed into the rest of the CPU should be fairly
trivial, so really they're just being retrieved. With the DPRINTF in
this new position, it will only trigger when an instruction is actually
decoded from memory.

Change-Id: I14145165b93bb004057a729fa7909cd2d3d34d29
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40099
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/decoder.hh
src/arch/mips/decoder.hh
src/arch/power/decoder.hh
src/arch/riscv/decoder.cc
src/arch/sparc/decoder.hh
src/arch/x86/decoder.cc
src/cpu/simple/base.cc