misc: Using smart pointers for memory Requests
authorGiacomo Travaglini <giacomo.travaglini@arm.com>
Mon, 4 Jun 2018 08:40:19 +0000 (09:40 +0100)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Mon, 11 Jun 2018 16:55:30 +0000 (16:55 +0000)
commitf54020eb8155371725ab75b0fc5c419287eca084
tree65d379f7603e689e083e9a58ff4c2e90abd19fbf
parent2113b21996d086dab32b9fd388efe3df241bfbd2
misc: Using smart pointers for memory Requests

This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.

Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
103 files changed:
ext/sst/ExtMaster.cc
ext/sst/ExtSlave.cc
src/arch/alpha/locked_mem.hh
src/arch/alpha/tlb.cc
src/arch/alpha/tlb.hh
src/arch/arm/isa.cc
src/arch/arm/locked_mem.hh
src/arch/arm/stage2_lookup.cc
src/arch/arm/stage2_lookup.hh
src/arch/arm/stage2_mmu.cc
src/arch/arm/stage2_mmu.hh
src/arch/arm/table_walker.cc
src/arch/arm/table_walker.hh
src/arch/arm/tlb.cc
src/arch/arm/tlb.hh
src/arch/arm/tracers/tarmac_parser.cc
src/arch/arm/tracers/tarmac_parser.hh
src/arch/arm/vtophys.cc
src/arch/generic/locked_mem.hh
src/arch/generic/tlb.cc
src/arch/generic/tlb.hh
src/arch/hsail/insts/mem.hh
src/arch/mips/locked_mem.hh
src/arch/mips/tlb.cc
src/arch/mips/tlb.hh
src/arch/power/tlb.cc
src/arch/power/tlb.hh
src/arch/riscv/locked_mem.hh
src/arch/riscv/tlb.cc
src/arch/riscv/tlb.hh
src/arch/sparc/tlb.cc
src/arch/sparc/tlb.hh
src/arch/x86/intmessage.hh
src/arch/x86/pagetable_walker.cc
src/arch/x86/pagetable_walker.hh
src/arch/x86/tlb.cc
src/arch/x86/tlb.hh
src/cpu/base.cc
src/cpu/base_dyn_inst.hh
src/cpu/base_dyn_inst_impl.hh
src/cpu/checker/cpu.cc
src/cpu/checker/cpu.hh
src/cpu/checker/cpu_impl.hh
src/cpu/kvm/base.cc
src/cpu/kvm/x86_cpu.cc
src/cpu/minor/fetch1.cc
src/cpu/minor/fetch1.hh
src/cpu/minor/lsq.cc
src/cpu/minor/lsq.hh
src/cpu/o3/cpu.hh
src/cpu/o3/fetch.hh
src/cpu/o3/fetch_impl.hh
src/cpu/o3/lsq.hh
src/cpu/o3/lsq_impl.hh
src/cpu/o3/lsq_unit.hh
src/cpu/o3/lsq_unit_impl.hh
src/cpu/simple/atomic.cc
src/cpu/simple/atomic.hh
src/cpu/simple/base.cc
src/cpu/simple/base.hh
src/cpu/simple/timing.cc
src/cpu/simple/timing.hh
src/cpu/testers/directedtest/InvalidateGenerator.cc
src/cpu/testers/directedtest/RubyDirectedTester.cc
src/cpu/testers/directedtest/SeriesRequestGenerator.cc
src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
src/cpu/testers/memtest/memtest.cc
src/cpu/testers/rubytest/Check.cc
src/cpu/testers/rubytest/RubyTester.cc
src/cpu/testers/traffic_gen/base_gen.cc
src/cpu/testers/traffic_gen/traffic_gen.cc
src/cpu/trace/trace_cpu.cc
src/cpu/translation.hh
src/dev/dma_device.cc
src/dev/x86/i82094aa.cc
src/gpu-compute/compute_unit.cc
src/gpu-compute/fetch_unit.cc
src/gpu-compute/gpu_tlb.cc
src/gpu-compute/gpu_tlb.hh
src/gpu-compute/shader.cc
src/gpu-compute/shader.hh
src/learning_gem5/part2/simple_cache.cc
src/mem/abstract_mem.cc
src/mem/abstract_mem.hh
src/mem/cache/base.cc
src/mem/cache/blk.hh
src/mem/cache/cache.cc
src/mem/cache/mshr.cc
src/mem/cache/noncoherent_cache.cc
src/mem/cache/prefetch/queued.cc
src/mem/packet.hh
src/mem/page_table.cc
src/mem/page_table.hh
src/mem/port.cc
src/mem/port_proxy.cc
src/mem/request.hh
src/mem/ruby/slicc_interface/AbstractController.cc
src/mem/ruby/system/CacheRecorder.cc
src/mem/ruby/system/GPUCoalescer.cc
src/mem/ruby/system/GPUCoalescer.hh
src/mem/ruby/system/RubyPort.cc
src/mem/ruby/system/Sequencer.cc
util/tlm/src/sc_master_port.cc