arch-power: Fix disassembly for branch instructions

This fixes disassembly generated for branch instructions
based on the AA and LK bits which determine how the target
address is calculated and whether a return address needs
to be set implicitly or not.

Change-Id: I1acba72c360a1fcb4691de17fbae1a012a752dbe
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
index 26a3c7481af22cc1d303240071fc6cf86c913e31..3747bf1b73c1dbc6f5b556755eb7e2391e3d5a29 100644 (file)
--- a/src/arch/power/insts/branch.cc
+++ b/src/arch/power/insts/branch.cc
@@ -71,7 +71,13 @@ BranchOp::generateDisassembly(
     std::stringstream ss;
     Addr target;
 
-    ccprintf(ss, "%-10s ", mnemonic);
+    // Generate correct mnemonic
+    std::string myMnemonic(mnemonic);
+
+    // Additional characters depending on isa bits being set
+    if (lkSet) myMnemonic = myMnemonic + "l";
+    if (aaSet) myMnemonic = myMnemonic + "a";
+    ccprintf(ss, "%-10s ", myMnemonic);
 
     if (aaSet) {
         target = disp;
@@ -107,7 +113,13 @@ BranchDispCondOp::generateDisassembly(
     std::stringstream ss;
     Addr target;
 
-    ccprintf(ss, "%-10s ", mnemonic);
+    // Generate the correct mnemonic
+    std::string myMnemonic(mnemonic);
+
+    // Additional characters depending on isa bits being set
+    if (lkSet) myMnemonic = myMnemonic + "l";
+    if (aaSet) myMnemonic = myMnemonic + "a";
+    ccprintf(ss, "%-10s ", myMnemonic);
 
     // Print BI and BO fields
     ss << crBit << ", " << opts << ", ";
@@ -142,6 +154,11 @@ BranchRegCondOp::generateDisassembly(
 {
     std::stringstream ss;
 
+    // Generate the correct mnemonic
+    std::string myMnemonic(mnemonic);
+
+    // Additional characters depending on isa bits being set
+    if (lkSet) myMnemonic = myMnemonic + "l";
     ccprintf(ss, "%-10s ", mnemonic);
 
     // Print the BI and BO fields