arch-power: Add byte order attribute for PC state

This adds byte order as an attribute for PC state by
introducing a new PCState class. The decoder can now
fetch instructions bytes in the specified byte order
in preparation for multi-mode support.

Change-Id: I917333df88114a733cc5a8077cc420d5328f608b
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

diff --git a/src/arch/power/decoder.hh b/src/arch/power/decoder.hh
index 4e02ef7bca0d496a0e3037cdcc8a2de1f728052c..c30014cce79fab1379830b4d0ec10127a55c2250 100644 (file)
--- a/src/arch/power/decoder.hh
+++ b/src/arch/power/decoder.hh
@@ -67,7 +67,7 @@ class Decoder : public InstDecoder
     void
     moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
     {
-        emi = betoh(inst);
+        emi = gtoh(inst, pc.byteOrder());
         instDone = true;
     }
 

diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh
index a76e6e29feeb4ac10ad2c45093a4a6147f4f22b2..c5a8f0fd1e9256f66844d0e06dcd9f69470db66c 100644 (file)
--- a/src/arch/power/types.hh
+++ b/src/arch/power/types.hh
@@ -32,6 +32,7 @@
 #include "arch/generic/types.hh"
 #include "base/bitunion.hh"
 #include "base/types.hh"
+#include "enums/ByteOrder.hh"
 
 namespace PowerISA
 {
@@ -94,7 +95,40 @@ BitUnion32(ExtMachInst)
     Bitfield<19, 12> fxm;
 EndBitUnion(ExtMachInst)
 
-typedef GenericISA::SimplePCState<MachInst> PCState;
+class PCState : public GenericISA::SimplePCState<MachInst>
+{
+  private:
+    typedef GenericISA::SimplePCState<MachInst> Base;
+    ByteOrder guestByteOrder = ByteOrder::big;
+
+  public:
+    PCState()
+    {}
+
+    void
+    set(Addr val)
+    {
+        Base::set(val);
+        npc(val + sizeof(MachInst));
+    }
+
+    PCState(Addr val)
+    {
+        set(val);
+    }
+
+    ByteOrder
+    byteOrder() const
+    {
+        return guestByteOrder;
+    }
+
+    void
+    byteOrder(ByteOrder order)
+    {
+        guestByteOrder = order;
+    }
+};
 
 // typedef uint64_t LargestRead;
 // // Need to use 64 bits to make sure that read requests get handled properly