arch-power: Add fields for DX form instructions

This introduces the extended opcode field for DS form
instructions and the fields d0, d1 and d2 which are
concatenated for specifying a signed integer immediate
operand.

Change-Id: Id60e85d79f9157d680f813bf90ab6e1e064253a9
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

diff --git a/src/arch/power/isa/bitfields.isa b/src/arch/power/isa/bitfields.isa
index 771a822583f337d40235a135a0aa77fee09d6565..84a3a2cfe4a5229120b0b8645598f4753d74003a 100644 (file)
--- a/src/arch/power/isa/bitfields.isa
+++ b/src/arch/power/isa/bitfields.isa
@@ -37,6 +37,7 @@
 def bitfield PO            <31:26>;
 def bitfield A_XO          <5:1>;
 def bitfield DS_XO         <1:0>;
+def bitfield DX_XO         <5:1>;
 def bitfield X_XO          <10:1>;
 def bitfield XFL_XO        <10:1>;
 def bitfield XFX_XO        <10:1>;

diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh
index 910c5f52f2f18cc80d8ed7e98300e24e03c74189..ef9b35fd8dfcef3eb72094edbe5db02d5b34ecb4 100644 (file)
--- a/src/arch/power/types.hh
+++ b/src/arch/power/types.hh
@@ -53,6 +53,9 @@ BitUnion32(ExtMachInst)
     Bitfield<15,  0> si;
     Bitfield<15,  0> d;
     Bitfield<15,  2> ds;
+    Bitfield<15,  6> d0;
+    Bitfield<20, 16> d1;
+    Bitfield< 1,  0> d2;
 
     // Special purpose register identifier
     Bitfield<20, 11> spr;