Kevin Lim [Tue, 30 May 2006 18:17:41 +0000 (14:17 -0400)]
Merge ktlim@zizzer:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
SConstruct:
src/SConscript:
src/arch/SConscript:
src/arch/alpha/faults.cc:
src/arch/alpha/tlb.cc:
src/base/traceflags.py:
src/cpu/SConscript:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.cc:
src/cpu/cpu_exec_context.cc:
src/cpu/cpu_exec_context.hh:
src/cpu/exec_context.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/regfile.hh:
src/cpu/ozone/cpu.hh:
src/cpu/simple/base.cc:
src/cpu/base_dyn_inst.hh:
src/cpu/o3/2bit_local_pred.cc:
src/cpu/o3/2bit_local_pred.hh:
src/cpu/o3/alpha_cpu.cc:
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_dyn_inst.cc:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/alpha_impl.hh:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/bpred_unit.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/btb.cc:
src/cpu/o3/btb.hh:
src/cpu/o3/comm.hh:
src/cpu/o3/commit.cc:
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu_policy.hh:
src/cpu/o3/decode.cc:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.cc:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/free_list.cc:
src/cpu/o3/free_list.hh:
src/cpu/o3/iew.cc:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.cc:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/mem_dep_unit.hh:
src/cpu/o3/mem_dep_unit_impl.hh:
src/cpu/o3/ras.cc:
src/cpu/o3/ras.hh:
src/cpu/o3/rename.cc:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rename_map.cc:
src/cpu/o3/rename_map.hh:
src/cpu/o3/rob.cc:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
src/cpu/o3/sat_counter.cc:
src/cpu/o3/sat_counter.hh:
src/cpu/o3/store_set.cc:
src/cpu/o3/store_set.hh:
src/cpu/o3/tournament_pred.cc:
src/cpu/o3/tournament_pred.hh:
Hand merges.
--HG--
rename : build/SConstruct => SConstruct
rename : SConscript => src/SConscript
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/pal.isa => src/arch/alpha/isa/pal.isa
rename : base/traceflags.py => src/base/traceflags.py
rename : cpu/SConscript => src/cpu/SConscript
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst.cc
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/cpu_exec_context.cc => src/cpu/cpu_exec_context.cc
rename : cpu/cpu_exec_context.hh => src/cpu/cpu_exec_context.hh
rename : cpu/cpu_models.py => src/cpu/cpu_models.py
rename : cpu/exec_context.hh => src/cpu/exec_context.hh
rename : cpu/exetrace.cc => src/cpu/exetrace.cc
rename : cpu/exetrace.hh => src/cpu/exetrace.hh
rename : cpu/inst_seq.hh => src/cpu/inst_seq.hh
rename : cpu/o3/2bit_local_pred.cc => src/cpu/o3/2bit_local_pred.cc
rename : cpu/o3/2bit_local_pred.hh => src/cpu/o3/2bit_local_pred.hh
rename : cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha_cpu.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha_cpu_builder.cc
rename : cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha_cpu_impl.hh
rename : cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha_dyn_inst.hh
rename : cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/o3/alpha_impl.hh => src/cpu/o3/alpha_impl.hh
rename : cpu/o3/alpha_params.hh => src/cpu/o3/alpha_params.hh
rename : cpu/o3/bpred_unit.cc => src/cpu/o3/bpred_unit.cc
rename : cpu/o3/bpred_unit.hh => src/cpu/o3/bpred_unit.hh
rename : cpu/o3/bpred_unit_impl.hh => src/cpu/o3/bpred_unit_impl.hh
rename : cpu/o3/btb.cc => src/cpu/o3/btb.cc
rename : cpu/o3/btb.hh => src/cpu/o3/btb.hh
rename : cpu/o3/comm.hh => src/cpu/o3/comm.hh
rename : cpu/o3/commit.cc => src/cpu/o3/commit.cc
rename : cpu/o3/commit.hh => src/cpu/o3/commit.hh
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/cpu.hh => src/cpu/o3/cpu.hh
rename : cpu/o3/cpu_policy.hh => src/cpu/o3/cpu_policy.hh
rename : cpu/o3/decode.cc => src/cpu/o3/decode.cc
rename : cpu/o3/decode.hh => src/cpu/o3/decode.hh
rename : cpu/o3/decode_impl.hh => src/cpu/o3/decode_impl.hh
rename : cpu/o3/fetch.cc => src/cpu/o3/fetch.cc
rename : cpu/o3/fetch.hh => src/cpu/o3/fetch.hh
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/free_list.cc => src/cpu/o3/free_list.cc
rename : cpu/o3/free_list.hh => src/cpu/o3/free_list.hh
rename : cpu/o3/iew.cc => src/cpu/o3/iew.cc
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.cc => src/cpu/o3/inst_queue.cc
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/mem_dep_unit.cc => src/cpu/o3/mem_dep_unit.cc
rename : cpu/o3/mem_dep_unit.hh => src/cpu/o3/mem_dep_unit.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/ras.cc => src/cpu/o3/ras.cc
rename : cpu/o3/ras.hh => src/cpu/o3/ras.hh
rename : cpu/o3/regfile.hh => src/cpu/o3/regfile.hh
rename : cpu/o3/rename.cc => src/cpu/o3/rename.cc
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/rename_map.cc => src/cpu/o3/rename_map.cc
rename : cpu/o3/rename_map.hh => src/cpu/o3/rename_map.hh
rename : cpu/o3/rob.hh => src/cpu/o3/rob.hh
rename : cpu/o3/rob_impl.hh => src/cpu/o3/rob_impl.hh
rename : cpu/o3/sat_counter.hh => src/cpu/o3/sat_counter.hh
rename : cpu/o3/store_set.cc => src/cpu/o3/store_set.cc
rename : cpu/o3/store_set.hh => src/cpu/o3/store_set.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/ozone/cpu.cc => src/cpu/ozone/cpu.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/static_inst.hh => src/cpu/static_inst.hh
rename : kern/system_events.cc => src/kern/system_events.cc
rename : kern/tru64/tru64.hh => src/kern/tru64/tru64.hh
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaFullCPU.py
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
extra : convert_revision :
ff351fc0e3a7c0f23e59fdbec33d8209eb9280be
Steve Reinhardt [Tue, 30 May 2006 10:34:26 +0000 (06:34 -0400)]
Fix SCons version check.
SConstruct:
Handle SCons version check error when running
on SCons 0.96 and previous.
--HG--
extra : convert_revision :
37595a468a9b56336c3f88a1057706f89bee9157
Ali Saidi [Mon, 29 May 2006 22:25:02 +0000 (18:25 -0400)]
commit a couple of minor things that I forgot to last time.
src/SConscript:
src/arch/sparc/SConscript:
commit a couple of things that I forgot to last time.
--HG--
extra : convert_revision :
f140912905b9d36eccc27e35ebcaf2c15611b56b
Ali Saidi [Mon, 29 May 2006 22:24:27 +0000 (18:24 -0400)]
Create a new CpuEvent class that has a pointer to an execution context in the object and places itself on a global list so
so the events can be migrated on cpu switches.
Create a new wrapper classe called CpuEventWrapper that works like the old wrapper class but calls the function with the xc
parameter
Use new CpuEventWrapper class from tick compare events on sparc
src/arch/sparc/regfile.hh:
Use new CpuEventWrapper class from tick compare events
src/arch/sparc/ua2005.cc:
Move definition to to a fullsystem only file, since it is.
src/cpu/base.cc:
On switch from one cpu to another CpuEvent::replaceExecContext() needs to be called on all (oldxc,newxc) pairs.
--HG--
extra : convert_revision :
eecf4540427cc0ddf75e19a3371cf32b56cba0f5
Ali Saidi [Mon, 29 May 2006 20:53:47 +0000 (16:53 -0400)]
split off fullsystem and se iprs into two functions to remove lots of #ifs
setup all initialization stuff for UA2005
Setup fullsys build options
Start to make fullsystem compile
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
RCS to BitKeeper
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Add support for doing virtual to physical translation using the in-memory
page table
src/arch/sparc/vtophys.cc:
a tad bit of error checking
src/arch/sparc/vtophys.hh:
Cleanup of full-system global variables, primarily in simple_cpu.cc,
to allow multi-system simulations. (Multiple systems not yet yested
though.) Also changes to build sim_smt in full-system mode (though
with only SimpleCPU and not the full timing CPU for now).
Still to do: minimize changes in SimpleCPU code between full-system
and application modes... way too many ifdefs there. Much of the
full-system stuff moved into SimpleCPU should be put in a new System
object to allow multiprocessor simulations.
Converted last remaining modules from C to C++ (mostly in /old).
Renamed all .c files to .cc and a few .h files to .hh.
Renamed architecture-specific files in arch/$TARGET from
$TARGET.{cc,hh,def} to machine.{cc,hh,def} to get rid of pointless
intermediate files in object directory. Split exo-specific
definitions out of machine.hh into machine_exo.h.
Specifics:
In machine.def, null resource descriptors must be FUClamd_NA (and not
NA) to pass C++ type checking.
Enhanced error checking/reporting in bas
src/arch/sparc/vtophys.cc:
- Get rid of my String class, the Vector class, the bitvector class, and my
doubly linked list class.
- Convert tokenize, to_number (formerly StringToNumber) and eat_white to
function on stl strings.
- Change most cases of char * and const char * to string, or const string &
- Some formatting and style nits, but not too many.
src/arch/sparc/vtophys.cc:
simplify
src/arch/sparc/vtophys.cc:
Renamed SimpleCPU::(read|write)_(byte|half|word|qword) to just read &
write, overloaded on the type of the 'data' argument. Merged the
full-system and non-full-system implementations of these eight
original functions into two common template functions.
To support this, also renamed (read|write)[1248] on memory_object and
derivatives to just read & write, again overloaded on the type of the
'data' argument. Many of these functions could now be condensed into
a few template functions (though with a level of indirection so that
the interface can remain virtual). I did not do that though.
src/arch/sparc/vtophys.cc:
First pass at compiling with gcc 3.x. Lots of "std::" in header files,
"using namespace std" in source files. (Note policy of not putting "using"
statements in headers or before includes in sources.)
Still not able to compile with gcc 3.2.
Errors:
- Can't create an ifstream from a file descriptor anymore (breaks IniFile).
- "`class MSHR::MSHRegister' is private" errors in mshr.cc and prefetch_cache.cc:
not clear why since it's in the public part of the class declaration.
- cpu.cc:879: can't match a reference and 0 (specifically "no match for `bool ?
SimObjectParam<PipeTrace*>& : int' operator")
- pipetrace.cc: "invalid conversion from `int' to `std::_Ios_Fmtflags'"
Warnings:
- strstream now deprecated... needs some rewriting in sat_counter.hh
and hybrid_pred.hh (need to get all that code out of the headers anyway)
- trace.hh macro problem: cpp now says 'pasting "::" and "Event" does not
give a valid preprocessing token'
- major "implicit typename" issues in base/sized.hh
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Implement some interval statistics for full system mode.
Create a callpal function that is called when a callpal occurs so it's easier
to manipulate the statics.
Rework the vtophys stuff to make it a bit cleaner.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Get rid of almost all old-style object names. This commit is equivalent
to running the following script on the current head:
#! /bin/sh
find \( -name '*.cc' -o -name '*.hh' \) -exec perl -pi -e '\
s/\bmemory_object\b(?!\.hh)/FunctionalMemory/g;\
s/\bvirtual_memory\b(?!\.hh)/VirtualMemory/g;\
s/\bmain_memory\b(?!\.hh)/MainMemory/g;\
s/\bphysical_memory\b(?!\.hh)/PhysicalMemory/g;\
s/\bspec_memory\b(?!\.hh)/SpeculativeMemory/g;\
s/\bMemObj\b(?!\.hh)/TimingMemObj/g;\
s/\bmemory_translation\b(?!\.hh)/AddressTranslator/g;\
s/\balpha_tlb\b(?!\.hh)/AlphaTlb/g;\
s/\balpha_itb\b(?!\.hh)/AlphaItb/g;\
s/\balpha_dtb\b(?!\.hh)/AlphaDtb/g;\
s/\bmemory_controller\b(?!\.hh)/MemoryController/g;\
s/\bstorebuffer_t\b(?!\.hh)/StoreBuffer/g;\
s/\bstorebuffer_entry_t\b(?!\.hh)/StoreBufferEntry/g;\
s/\bcreate_vector_t\b(?!\.hh)/CreateVector/g;\
s/\bcv_spec_state\b(?!\.hh)/CreateVecSpecState/g;\
s/\bspec_state_list\b(?!\.hh)/SpecStateList/g;\
s/\bdyn_inst_t\b(?!\.hh)/DynInst/g;' {} \;
src/arch/sparc/vtophys.cc:
since cprintf properly deals with 64-bit types, stop using FMT* as much as
possible
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Change byte_t etc. to C99 standard int8_t etc.
Other than old/host.h, all other changes were produced by this script:
#! /bin/sh
find \( -name '*.cc' -o -name '*.hh' -o -name '*.c' -o -name '*.h' -o -name 'machine.def' \) -exec perl -pi -e '\
s/\bbyte_t\b(?!\.hh)/uint8_t/g;\
s/\bsbyte_t\b(?!\.hh)/int8_t/g;\
s/\bhalf_t\b(?!\.hh)/uint16_t/g;\
s/\bshalf_t\b(?!\.hh)/int16_t/g;\
s/\bword_t\b(?!\.hh)/uint32_t/g;\
s/\bsword_t\b(?!\.hh)/int32_t/g;\
s/\bqword_t\b(?!\.hh)/uint64_t/g;\
s/\bsqword_t\b(?!\.hh)/int64_t/g;\
s/\bbool_t\b(?!\.hh)/bool/g;\
s/\bdfloat_t\b(?!\.hh)/double/g;\
s/\bsfloat_t\b(?!\.hh)/float/g;' {} \;
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Add CVS Id tags
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Massive renaming to (almost) eliminate all md_* and MD_* names
in preparation for total exorcism of machine.def.
Most of the changes in this commit were performed with the
following perl script (perl -pi <script> <files>). A small
amount of manual fixup was needed to (mostly getting rid of
the Addr typedefs in the various memory objects now that
the former md_addr_t has that name).
# rename machine-dependent types and constants (will be moving into ISA traits object)
s/md_addr_t/Addr/g;
s/md_intreg_t/IntReg/g;
s/md_gpr_t/IntRegFile/g;
s/md_fpreg_t/FloatReg/g;
s/md_fpr_t/FloatRegFile/g;
s/md_ctrlreg_t/MiscReg/g;
s/md_ctrl_t/MiscRegFile/g;
s/md_ipr_t/InternalProcReg/g;
s/md_anyreg_t/AnyReg/g;
s/md_inst_t/MachInst/g;
s/regs_t/RegFile/g;
# manually fix declaration in old/regs.h and a few forward decls
s/struct RegFile/RegFile/g;
s/MD_NUM_IREGS/NumIntRegs/g;
s/MD_NUM_FREGS/NumFloatRegs/g;
s/MD_NUM_CREGS/NumMiscRegs/g;
s/MD_IPR_NUM/NumInternalProcRegs/g;
s/MD_TOTAL_REGS/TotalNumRegs/g;
s/MD_REG_ZERO/ZeroReg/g;
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
New ISA description system. No more machine.def!
Instructions are now decoded into StaticInst objects, and all static
instruction properties (including execution behavior) are associated
with those objects. Extended documentation in progress.
Currently supports Alpha only; PISA will not compile.
Use END_OF_MACHINE_DOT_DEF tag to extract previous version.
src/arch/sparc/vtophys.cc:
get rid of MD_IPR_foo and call it IPR_foo
add some comments to describe what the various PALtemp registers do
formatting
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
license
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
a little style
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Add attribution to license.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Make include paths explicit.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
CopyData and CopyString moved from kernel.cc to vtophys.cc
kernel.cc and kernel.hh moved to kern/tru64
src/arch/sparc/vtophys.hh:
Include isa_traits.hh for Addr
src/arch/sparc/vtophys.cc:
formatting fixes
src/arch/sparc/vtophys.cc:
fix up vtophys to deal with translations if there
is no ptbr, and to deal with PAL addresses
add ptomem which is just a wrapper for dma_addr
src/arch/sparc/vtophys.hh:
add ptomem which is a wrapper for dma_addr with the
same usage as vtomem
src/arch/sparc/vtophys.cc:
Fix to remote debugger while in PAL code
src/arch/sparc/vtophys.cc:
Remote an old hack that is now unnecessary
src/arch/sparc/vtophys.cc:
Removed buggy code that tries to fix PAL addresses (may cause problems
while trying to debug in PAL code, but that should do this fix outside
of vtophys)
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Updated Copyright
src/arch/sparc/vtophys.cc:
added back some code andrew removed and couldn't remember why.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
rename CopyData to CopyOut and implement CopyIn to copy data
from the simulator into the simulatee
src/arch/sparc/vtophys.cc:
fixed a bad merge from linux<->tru64
src/arch/sparc/vtophys.cc:
Check max address pal can be at so we don't do the wrong conversion
if gdb asks for an unaligned access.
src/arch/sparc/vtophys.cc:
PGOFSET -> ALPHA_PGOFSET to avoid include file problems
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
in the arch/alpha directory we should use arch/alpha, not
targetarch. sort includes while we're here.
src/arch/sparc/vtophys.cc:
use new constants, functions and structs to clean up the
vtophys code.
src/arch/sparc/vtophys.hh:
Clean up a little bit and make the protypes match new changes.
src/arch/sparc/vtophys.cc:
deal with isa addition
src/arch/sparc/vtophys.cc:
shuffle files around for new directory structure
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Remove RCS Id string
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Update copyright dates and author list
src/arch/sparc/vtophys.cc:
Added a using directive for AlphaISA
src/arch/sparc/vtophys.hh:
Added the AlphaISA namespace specifier where needed
src/arch/sparc/vtophys.hh:
Made Addr a global type
src/arch/sparc/vtophys.cc:
Change access to the IPR to go through the XC.
src/arch/sparc/vtophys.cc:
Avoid directly accessing objects within the XC.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
fixed for new memory system
put in namespace AlphaISA
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
Remove authors from copyright.
src/arch/sparc/vtophys.cc:
bk cp alpha/vtophys.cc sparc/vtophys.cc
src/arch/sparc/vtophys.hh:
bk cp alpha/vtophys.hh sparc/vtophys.hh
src/arch/sparc/SConscript:
remove fullsystem files that don't exist
src/arch/sparc/isa_traits.hh:
split off fullsystem and se iprs into two functions to remove lots of #ifs
src/arch/sparc/regfile.hh:
split off fullsystem and se iprs into two functions to remove lots of #ifs
setup all initialization stuff for UA2005
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
Add system level tick storage to make stick be syncronized across multiple processors
src/arch/sparc/vtophys.hh:
start to create a vtophys for Sparc
src/base/loader/symtab.hh:
Addr is defined in sim/host.hh
--HG--
extra : convert_revision :
ae4658e6bc2e2b51d7fb1c711d069ffe99e1377d
Ali Saidi [Mon, 29 May 2006 03:26:15 +0000 (23:26 -0400)]
Remove authors from copyright.
--HG--
extra : convert_revision :
5daba0ab70b4e6d7213bad6aedcb47a0fe56031d
Ali Saidi [Mon, 29 May 2006 02:21:57 +0000 (22:21 -0400)]
remove some getPtr() calls by changing having function return values
instead of taking a pointer
--HG--
extra : convert_revision :
fd9092eaa726e91b501334d35d28dda28aaa01bd
Ali Saidi [Fri, 26 May 2006 22:40:08 +0000 (18:40 -0400)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
3a34dbab3101281786a4b70724c5aee3e4730843
Ali Saidi [Fri, 26 May 2006 22:40:00 +0000 (18:40 -0400)]
Implement PR/HPR/ASR for full system
Rip out storage in miscreg file that will never store anything
Add storage and defines for Priv and Hyperpriv registers
Change defines to match the spec register numbers
Change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR.
Change contextval to an int since both global registers and windowed registers are indexed by int in UA2005.
Use bitfields for things that are rarely used in decoder
Instead of decoding ASR/PR/HPR and having a specfic instruction, use a generic instruction instead
Still todo:
Protect rdpr, rdhpr, wrpr, wrhpr with checks that fault in insufficient privs
Deal with signaling interrupts on timer expiration
Deal with writes to softint/PIL generating interrupts how those are vectored to the CPU
Other misc:
Instruction decoding needs major help!
src/arch/sparc/isa/decoder.isa:
Remove tons of MISCREG_XXXX defines that weren't used and ControlRegs in that were never used. Ones that were used rarely
changed to bitfields.
src/arch/sparc/isa/formats/integerop.isa:
These seems like a whole lot of overkill in printing, but i'll leave it the way it is for now. Allow Ccr to be set
at once
src/arch/sparc/isa/formats/priv.isa:
PrivTick is handled by miscreg now, don't need a seperate class for it
src/arch/sparc/isa/operands.isa:
prune the number of control regs down to a reasonable amount
src/arch/sparc/isa_traits.hh:
Replace 8 defines with 1 and flick some bits
src/arch/sparc/process.cc:
Better to clean the entire registers that specific bits which leads to indetermanistic behavior.
src/arch/sparc/regfile.hh:
Rip out storage that will never be backed by anything
Add storage for Priv and Hyperpriv registers
change defines to match the spec
change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR.
change contextval to an int since both global registers and windowed registers are indexed by int in UA2005.
--HG--
extra : convert_revision :
64276a3ea884eea70112e721f85a515946ded4c2
Steve Reinhardt [Fri, 26 May 2006 18:33:43 +0000 (14:33 -0400)]
Fixes for TimingSimpleCPU under full system. Now boots Alpha Linux!
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
Move traceData->finalize() into postExecute().
src/cpu/simple/timing.cc:
Fixes for full system. Now boots Alpha Linux!
- Handle ifetch faults, suspend/resume.
- Delete memory request & packet objects on response.
- Don't try to do split memory accesses on prefetch references
(ISA description doesn't support this).
src/cpu/simple/timing.hh:
Minor reorganization of internal methods.
--HG--
extra : convert_revision :
59e3ee5e4cb53c424ebdbe2e504d97e88c08a978
Steve Reinhardt [Fri, 26 May 2006 18:29:29 +0000 (14:29 -0400)]
Reorganize bridge as pair of cooperating ports.
Store original source & senderState for timing packets
that get a response, so we can properly route the
response packet back to the original sender.
--HG--
extra : convert_revision :
03dbcc8dc06d93de243bfcdc3cbaa012773c6782
Steve Reinhardt [Fri, 26 May 2006 18:24:46 +0000 (14:24 -0400)]
Add a little more tracing support for Bus/Port stuff.
src/base/traceflags.py:
Sort flags so you can find things.
Add BusAddrRanges flag for tracking RangeChange events
separately from general bus activity.
src/mem/bus.cc:
Add BusAddrRanges flag for tracking RangeChange events
separately from general bus activity.
src/mem/port.cc:
src/mem/port.hh:
Print Config trace message when peers are set up.
--HG--
extra : convert_revision :
d7c11d5f90c8de5c8d97e473501a268a567e9e44
Steve Reinhardt [Fri, 26 May 2006 18:17:33 +0000 (14:17 -0400)]
Significant rework of Packet class interface:
- new constructor guarantees initialization of most fields
- flags track status of non-guaranteed fields (addr, size, src)
- accessor functions (getAddr() etc.) check status on access
- Command & Result classes are nested in Packet class scope
- Command now built from vector of behavior bits
- string version of Command for tracing
- reinitFromRequest() and makeTimingResponse() encapsulate
common manipulations of existing packets
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/timing.cc:
src/dev/alpha_console.cc:
src/dev/ide_ctrl.cc:
src/dev/io_device.cc:
src/dev/io_device.hh:
src/dev/isa_fake.cc:
src/dev/ns_gige.cc:
src/dev/pciconfigall.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/dev/tsunami_io.cc:
src/dev/tsunami_pchip.cc:
src/dev/uart8250.cc:
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/physical.cc:
src/mem/port.cc:
src/mem/port.hh:
src/mem/request.hh:
Update for new Packet interface.
--HG--
extra : convert_revision :
9973d09ea4fa61795f23772a7d3995fa4df5c269
Steve Reinhardt [Fri, 26 May 2006 17:48:35 +0000 (13:48 -0400)]
Add names to memory Port objects for tracing.
--HG--
extra : convert_revision :
ddf30084e343e8656e4812ab20356292b35507ee
Kevin Lim [Thu, 25 May 2006 21:56:01 +0000 (17:56 -0400)]
Fix stat typo.
--HG--
extra : convert_revision :
f23d8c50f586fb8f25d4ce992730213f0c301b0f
Kevin Lim [Thu, 25 May 2006 15:50:42 +0000 (11:50 -0400)]
Fix up kernel stats, allow them to not be used as well.
arch/alpha/ev5.cc:
Fix up some stuff I missed in the last kernel stats checkin.
cpu/checker/cpu.cc:
Allow the checker to disable its kernel stats.
cpu/cpu_exec_context.cc:
Allow CPUExecContext to be created without kernelStats.
cpu/cpu_exec_context.hh:
Allow CPUExecContext to be created without kernelStats. Default usage leaves kernelStats on.
--HG--
extra : convert_revision :
8ed5bffd3a5b6275baa07fb4ea385eeab1a0456a
Kevin Lim [Wed, 24 May 2006 18:31:06 +0000 (14:31 -0400)]
Support new flags now used instead of flags in decoder.isa.
cpu/ozone/front_end_impl.hh:
cpu/ozone/lw_back_end_impl.hh:
cpu/ozone/lw_lsq_impl.hh:
Support new flags added in.
--HG--
extra : convert_revision :
2e756fd1913cf600650afc39dd715d59b9b89c42
Kevin Lim [Tue, 23 May 2006 22:19:04 +0000 (18:19 -0400)]
Merge ktlim@zizzer:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-o3
--HG--
extra : convert_revision :
804302a5edb9d908808861f7f54a4f3cbb22830c
Kevin Lim [Tue, 23 May 2006 22:18:16 +0000 (18:18 -0400)]
Updates to isa parser to make it see dependencies properly with the new scanner.
arch/alpha/isa/main.isa:
Use automatic path includes thanks to updates to isa parser.
arch/isa_parser.py:
Pull changes to isa parser from newmem into m5. This fixes a bug where the files include in main.isa were not being included as dependencies properly.
--HG--
extra : convert_revision :
8ef1e2e1a64e7a5762baf7a09abc8665d7c2f688
Steve Reinhardt [Tue, 23 May 2006 21:16:45 +0000 (17:16 -0400)]
Minor fixes for full-system timing memory.
Need to rewrite bus bridge to get any further.
src/dev/io_device.cc:
Set packet dest on timing responses.
src/mem/bus.cc:
Fix dest addr bounds check assertion.
Add assertion to catch infinite loopbacks.
src/mem/physical.cc:
Add comment.
--HG--
extra : convert_revision :
419b65a3a61e2d099884dbda117b338dffd80896
Kevin Lim [Tue, 23 May 2006 21:04:25 +0000 (17:04 -0400)]
Merge ktlim@zizzer:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-o3
--HG--
extra : convert_revision :
0a6140f3f5e7c454981c5aa2b221224f076e50eb
Kevin Lim [Tue, 23 May 2006 21:03:43 +0000 (17:03 -0400)]
Rework how instructions are scheduled and executed.
The "execute" portion of IEW is really just the last cycle of execution, at which point execute() gets called. Execution begins inside the IQ, when it schedules FUs for specific instructions. As a result, the Execute stage should just pull all completing instructions out of the IQ stage and execute them.
Limiting the number of writebacks outstanding must still be done.
cpu/o3/iew_impl.hh:
Rework how instructions are scheduled and executed. There shouldn't be a specific "width" from issue to execute because issue does the scheduling of the functional units (really the beginning of the execution).
cpu/o3/inst_queue.hh:
cpu/o3/inst_queue_impl.hh:
Rework how instructions are scheduled and executed.
--HG--
extra : convert_revision :
bbf1a8a4c0a2f2a938bdd78d74493048fd3b4b55
Kevin Lim [Tue, 23 May 2006 20:59:13 +0000 (16:59 -0400)]
Cleanup checker.
cpu/checker/cpu.cc:
Cleanup checker, give more useful warning messages.
Also fix bug
cpu/checker/cpu.hh:
Cleanup checker, use forward declaration instead of include.
--HG--
extra : convert_revision :
8f231199a0a75788218320cdbcc7f70441e5d574
Kevin Lim [Tue, 23 May 2006 20:57:14 +0000 (16:57 -0400)]
Code cleanup.
cpu/base_dyn_inst.hh:
Code cleanup
--HG--
extra : convert_revision :
501c03f8e4346ffbcb545ddeee30c1f8ded9baa7
Kevin Lim [Tue, 23 May 2006 20:51:16 +0000 (16:51 -0400)]
Move kernel stats out of CPU and into XC.
arch/alpha/ev5.cc:
Move kernel stats out of CPU and into XC. Also be sure to check if the kernel stats exist prior to using them.
--HG--
extra : convert_revision :
565cd7026410fd7d8586f953d9b328c2e67a9473
Kevin Lim [Tue, 23 May 2006 18:38:16 +0000 (14:38 -0400)]
Add extra flags to help new CPU handle various instructions.
IsIprAccess flag may go away in the future (op class can be used to tell this), and the CPU still needs a specific way to identify/deal with syscalls.
arch/alpha/isa/decoder.isa:
Added a few extra flags to help the new CPU identify various classes of instructions without having to force certain behaviors for all CPUs.
cpu/base_dyn_inst.hh:
cpu/static_inst.hh:
Added extra flags.
cpu/o3/iew_impl.hh:
cpu/o3/inst_queue_impl.hh:
Handle store conditionals specially.
cpu/o3/lsq_unit_impl.hh:
Extra flags tells if the instruction is a store conditional.
cpu/o3/rename_impl.hh:
Handle IPR accesses and store conditionals specially.
--HG--
extra : convert_revision :
39debec4fa5341ae8a8ab5650bd12730aeb6c04f
Steve Reinhardt [Tue, 23 May 2006 02:37:56 +0000 (22:37 -0400)]
Make scons auto-configure stuff per-build-root.
Undo changes to allow multiple build roots in a single
invocation... this would have been too messy to maintain
with the auto-configure stuff, and probably isn't useful anyway.
--HG--
extra : convert_revision :
32a2d9d7fc980911acc3e7b9430df1ba5a0ee68e
Steve Reinhardt [Tue, 23 May 2006 02:18:08 +0000 (22:18 -0400)]
Get rid of FastCPU model.
It doesn't compile, and if we really want this we should
start over from scratch and see if we can reuse parts from
BaseSimpleCPU (e.g., derive a FastSimpleCPU).
SConstruct:
src/arch/SConscript:
src/cpu/cpu_models.py:
Get rid of FastCPU model.
--HG--
extra : convert_revision :
f3f0362f7292bf21e8e0d4d84c475be8a9789a0c
Steve Reinhardt [Tue, 23 May 2006 02:15:22 +0000 (22:15 -0400)]
Fix to SPARC Nop class for multiple CPU models.
src/arch/sparc/isa/formats/nop.isa:
Fix nop header so we can compile with multiple CPU models.
(Former code re-defined Nop object for each model.)
--HG--
extra : convert_revision :
04e92622edf4dfefd9e149a17f604e17a93707c9
Steve Reinhardt [Tue, 23 May 2006 02:14:10 +0000 (22:14 -0400)]
Make CPU_MODELS default to just the two SimpleCPU variants
for now (since those are the only ones that compile).
--HG--
extra : convert_revision :
d865afc0626e52bfa3ad1b4817f4530bcacef03e
Steve Reinhardt [Tue, 23 May 2006 01:51:59 +0000 (21:51 -0400)]
Clean up libelf handling.
SConstruct:
Clean up libelf handling. Required better handling of
per-build-root stuff in general (though libelf is the
only thing in that category currently).
src/SConscript:
No libelf-specific stuff in here anymore.
src/base/loader/elf_object.cc:
Just need to include gelf.h... it includes libelf.h.
--HG--
extra : convert_revision :
3d6bdcf8233bda0ac8d08ff777de323df8aa45ae
Ali Saidi [Mon, 22 May 2006 21:38:00 +0000 (17:38 -0400)]
have multiple global levels (as required by UA2005)
--HG--
extra : convert_revision :
027b89f3a42a2ba061e892d07aee768ff0afc49d
Kevin Lim [Mon, 22 May 2006 20:01:25 +0000 (16:01 -0400)]
Undo changes to instruction flags that has caused statistics to change in regressions.
This temporarily will break the O3 and Ozone CPU models. Updates to fix them will be coming soon.
arch/alpha/isa/decoder.isa:
Undo changes to instruction flags that has caused statistics to change in regressions.
--HG--
extra : convert_revision :
c0fa9d55a22cae7c4f02d388870565b205d6fba3
Steve Reinhardt [Mon, 22 May 2006 18:41:49 +0000 (14:41 -0400)]
Forgot to delete the now-obsolete mkbuilddir script.
--HG--
extra : convert_revision :
75bff38425789e30128fa33845fabde8848410fd
Steve Reinhardt [Mon, 22 May 2006 18:29:33 +0000 (14:29 -0400)]
New directory structure:
- simulator source now in 'src' subdirectory
- imported files from 'ext' repository
- support building in arbitrary places, including
outside of the source tree. See comment at top
of SConstruct file for more details.
Regression tests are temporarily disabled; that
syetem needs more extensive revisions.
SConstruct:
Update for new directory structure.
Modify to support build trees that are not subdirectories
of the source tree. See comment at top of file for
more details.
Regression tests are temporarily disabled.
src/arch/SConscript:
src/arch/isa_parser.py:
src/python/SConscript:
Update for new directory structure.
--HG--
rename : build/SConstruct => SConstruct
rename : build/default_options/ALPHA_FS => build_opts/ALPHA_FS
rename : build/default_options/ALPHA_FS_TL => build_opts/ALPHA_FS_TL
rename : build/default_options/ALPHA_SE => build_opts/ALPHA_SE
rename : build/default_options/MIPS_SE => build_opts/MIPS_SE
rename : build/default_options/SPARC_SE => build_opts/SPARC_SE
rename : Doxyfile => src/Doxyfile
rename : SConscript => src/SConscript
rename : arch/SConscript => src/arch/SConscript
rename : arch/alpha/SConscript => src/arch/alpha/SConscript
rename : arch/alpha/aout_machdep.h => src/arch/alpha/aout_machdep.h
rename : arch/alpha/arguments.cc => src/arch/alpha/arguments.cc
rename : arch/alpha/arguments.hh => src/arch/alpha/arguments.hh
rename : arch/alpha/ecoff_machdep.h => src/arch/alpha/ecoff_machdep.h
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/ev5.hh => src/arch/alpha/ev5.hh
rename : arch/alpha/faults.cc => src/arch/alpha/faults.cc
rename : arch/alpha/faults.hh => src/arch/alpha/faults.hh
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/freebsd/system.hh => src/arch/alpha/freebsd/system.hh
rename : arch/alpha/isa/branch.isa => src/arch/alpha/isa/branch.isa
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/fp.isa => src/arch/alpha/isa/fp.isa
rename : arch/alpha/isa/int.isa => src/arch/alpha/isa/int.isa
rename : arch/alpha/isa/main.isa => src/arch/alpha/isa/main.isa
rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa
rename : arch/alpha/isa/opcdec.isa => src/arch/alpha/isa/opcdec.isa
rename : arch/alpha/isa/pal.isa => src/arch/alpha/isa/pal.isa
rename : arch/alpha/isa/unimp.isa => src/arch/alpha/isa/unimp.isa
rename : arch/alpha/isa/unknown.isa => src/arch/alpha/isa/unknown.isa
rename : arch/alpha/isa/util.isa => src/arch/alpha/isa/util.isa
rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh
rename : arch/alpha/linux/aligned.hh => src/arch/alpha/linux/aligned.hh
rename : arch/alpha/linux/hwrpb.hh => src/arch/alpha/linux/hwrpb.hh
rename : arch/alpha/linux/linux.cc => src/arch/alpha/linux/linux.cc
rename : arch/alpha/linux/linux.hh => src/arch/alpha/linux/linux.hh
rename : arch/alpha/linux/process.cc => src/arch/alpha/linux/process.cc
rename : arch/alpha/linux/process.hh => src/arch/alpha/linux/process.hh
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/linux/system.hh => src/arch/alpha/linux/system.hh
rename : arch/alpha/linux/thread_info.hh => src/arch/alpha/linux/thread_info.hh
rename : arch/alpha/linux/threadinfo.hh => src/arch/alpha/linux/threadinfo.hh
rename : arch/alpha/osfpal.cc => src/arch/alpha/osfpal.cc
rename : arch/alpha/osfpal.hh => src/arch/alpha/osfpal.hh
rename : arch/alpha/process.cc => src/arch/alpha/process.cc
rename : arch/alpha/process.hh => src/arch/alpha/process.hh
rename : arch/alpha/regfile.hh => src/arch/alpha/regfile.hh
rename : arch/alpha/stacktrace.cc => src/arch/alpha/stacktrace.cc
rename : arch/alpha/stacktrace.hh => src/arch/alpha/stacktrace.hh
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/system.hh => src/arch/alpha/system.hh
rename : arch/alpha/tlb.cc => src/arch/alpha/tlb.cc
rename : arch/alpha/tlb.hh => src/arch/alpha/tlb.hh
rename : arch/alpha/tru64/process.cc => src/arch/alpha/tru64/process.cc
rename : arch/alpha/tru64/process.hh => src/arch/alpha/tru64/process.hh
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : arch/alpha/tru64/system.hh => src/arch/alpha/tru64/system.hh
rename : arch/alpha/tru64/tru64.cc => src/arch/alpha/tru64/tru64.cc
rename : arch/alpha/tru64/tru64.hh => src/arch/alpha/tru64/tru64.hh
rename : arch/alpha/types.hh => src/arch/alpha/types.hh
rename : arch/alpha/utility.hh => src/arch/alpha/utility.hh
rename : arch/alpha/vtophys.cc => src/arch/alpha/vtophys.cc
rename : arch/alpha/vtophys.hh => src/arch/alpha/vtophys.hh
rename : arch/isa_parser.py => src/arch/isa_parser.py
rename : arch/isa_specific.hh => src/arch/isa_specific.hh
rename : arch/mips/SConscript => src/arch/mips/SConscript
rename : arch/mips/faults.cc => src/arch/mips/faults.cc
rename : arch/mips/faults.hh => src/arch/mips/faults.hh
rename : arch/mips/isa/base.isa => src/arch/mips/isa/base.isa
rename : arch/mips/isa/bitfields.isa => src/arch/mips/isa/bitfields.isa
rename : arch/mips/isa/decoder.isa => src/arch/mips/isa/decoder.isa
rename : arch/mips/isa/formats/basic.isa => src/arch/mips/isa/formats/basic.isa
rename : arch/mips/isa/formats/branch.isa => src/arch/mips/isa/formats/branch.isa
rename : arch/mips/isa/formats/formats.isa => src/arch/mips/isa/formats/formats.isa
rename : arch/mips/isa/formats/fp.isa => src/arch/mips/isa/formats/fp.isa
rename : arch/mips/isa/formats/int.isa => src/arch/mips/isa/formats/int.isa
rename : arch/mips/isa/formats/mem.isa => src/arch/mips/isa/formats/mem.isa
rename : arch/mips/isa/formats/noop.isa => src/arch/mips/isa/formats/noop.isa
rename : arch/mips/isa/formats/tlbop.isa => src/arch/mips/isa/formats/tlbop.isa
rename : arch/mips/isa/formats/trap.isa => src/arch/mips/isa/formats/trap.isa
rename : arch/mips/isa/formats/unimp.isa => src/arch/mips/isa/formats/unimp.isa
rename : arch/mips/isa/formats/unknown.isa => src/arch/mips/isa/formats/unknown.isa
rename : arch/mips/isa/formats/util.isa => src/arch/mips/isa/formats/util.isa
rename : arch/mips/isa/includes.isa => src/arch/mips/isa/includes.isa
rename : arch/mips/isa/main.isa => src/arch/mips/isa/main.isa
rename : arch/mips/isa/operands.isa => src/arch/mips/isa/operands.isa
rename : arch/mips/isa_traits.cc => src/arch/mips/isa_traits.cc
rename : arch/mips/isa_traits.hh => src/arch/mips/isa_traits.hh
rename : arch/mips/linux/linux.cc => src/arch/mips/linux/linux.cc
rename : arch/mips/linux/linux.hh => src/arch/mips/linux/linux.hh
rename : arch/mips/linux/process.cc => src/arch/mips/linux/process.cc
rename : arch/mips/linux/process.hh => src/arch/mips/linux/process.hh
rename : arch/mips/process.cc => src/arch/mips/process.cc
rename : arch/mips/process.hh => src/arch/mips/process.hh
rename : arch/mips/regfile/float_regfile.hh => src/arch/mips/regfile/float_regfile.hh
rename : arch/mips/regfile/int_regfile.hh => src/arch/mips/regfile/int_regfile.hh
rename : arch/mips/regfile/misc_regfile.hh => src/arch/mips/regfile/misc_regfile.hh
rename : arch/mips/regfile/regfile.hh => src/arch/mips/regfile/regfile.hh
rename : arch/mips/stacktrace.hh => src/arch/mips/stacktrace.hh
rename : arch/mips/types.hh => src/arch/mips/types.hh
rename : arch/mips/utility.hh => src/arch/mips/utility.hh
rename : arch/sparc/SConscript => src/arch/sparc/SConscript
rename : arch/sparc/faults.cc => src/arch/sparc/faults.cc
rename : arch/sparc/faults.hh => src/arch/sparc/faults.hh
rename : arch/sparc/isa/base.isa => src/arch/sparc/isa/base.isa
rename : arch/sparc/isa/bitfields.isa => src/arch/sparc/isa/bitfields.isa
rename : arch/sparc/isa/decoder.isa => src/arch/sparc/isa/decoder.isa
rename : arch/sparc/isa/formats.isa => src/arch/sparc/isa/formats.isa
rename : arch/sparc/isa/formats/basic.isa => src/arch/sparc/isa/formats/basic.isa
rename : arch/sparc/isa/formats/branch.isa => src/arch/sparc/isa/formats/branch.isa
rename : arch/sparc/isa/formats/integerop.isa => src/arch/sparc/isa/formats/integerop.isa
rename : arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem.isa
rename : arch/sparc/isa/formats/nop.isa => src/arch/sparc/isa/formats/nop.isa
rename : arch/sparc/isa/formats/priv.isa => src/arch/sparc/isa/formats/priv.isa
rename : arch/sparc/isa/formats/trap.isa => src/arch/sparc/isa/formats/trap.isa
rename : arch/sparc/isa/formats/unknown.isa => src/arch/sparc/isa/formats/unknown.isa
rename : arch/sparc/isa/includes.isa => src/arch/sparc/isa/includes.isa
rename : arch/sparc/isa/main.isa => src/arch/sparc/isa/main.isa
rename : arch/sparc/isa/operands.isa => src/arch/sparc/isa/operands.isa
rename : arch/sparc/isa_traits.hh => src/arch/sparc/isa_traits.hh
rename : arch/sparc/linux/linux.cc => src/arch/sparc/linux/linux.cc
rename : arch/sparc/linux/linux.hh => src/arch/sparc/linux/linux.hh
rename : arch/sparc/linux/process.cc => src/arch/sparc/linux/process.cc
rename : arch/sparc/linux/process.hh => src/arch/sparc/linux/process.hh
rename : arch/sparc/process.cc => src/arch/sparc/process.cc
rename : arch/sparc/process.hh => src/arch/sparc/process.hh
rename : arch/sparc/regfile.hh => src/arch/sparc/regfile.hh
rename : arch/sparc/solaris/process.cc => src/arch/sparc/solaris/process.cc
rename : arch/sparc/solaris/process.hh => src/arch/sparc/solaris/process.hh
rename : arch/sparc/solaris/solaris.cc => src/arch/sparc/solaris/solaris.cc
rename : arch/sparc/solaris/solaris.hh => src/arch/sparc/solaris/solaris.hh
rename : arch/sparc/stacktrace.hh => src/arch/sparc/stacktrace.hh
rename : arch/sparc/system.cc => src/arch/sparc/system.cc
rename : arch/sparc/system.hh => src/arch/sparc/system.hh
rename : arch/sparc/utility.hh => src/arch/sparc/utility.hh
rename : base/bitfield.hh => src/base/bitfield.hh
rename : base/callback.hh => src/base/callback.hh
rename : base/chunk_generator.hh => src/base/chunk_generator.hh
rename : base/circlebuf.cc => src/base/circlebuf.cc
rename : base/circlebuf.hh => src/base/circlebuf.hh
rename : base/compression/lzss_compression.cc => src/base/compression/lzss_compression.cc
rename : base/compression/lzss_compression.hh => src/base/compression/lzss_compression.hh
rename : base/compression/null_compression.hh => src/base/compression/null_compression.hh
rename : base/cprintf.cc => src/base/cprintf.cc
rename : base/cprintf.hh => src/base/cprintf.hh
rename : base/cprintf_formats.hh => src/base/cprintf_formats.hh
rename : base/crc.cc => src/base/crc.cc
rename : base/crc.hh => src/base/crc.hh
rename : base/date.cc => src/base/date.cc
rename : base/dbl_list.hh => src/base/dbl_list.hh
rename : base/endian.hh => src/base/endian.hh
rename : base/fast_alloc.cc => src/base/fast_alloc.cc
rename : base/fast_alloc.hh => src/base/fast_alloc.hh
rename : base/fenv.hh => src/base/fenv.hh
rename : base/fifo_buffer.cc => src/base/fifo_buffer.cc
rename : base/fifo_buffer.hh => src/base/fifo_buffer.hh
rename : base/hashmap.hh => src/base/hashmap.hh
rename : base/hostinfo.cc => src/base/hostinfo.cc
rename : base/hostinfo.hh => src/base/hostinfo.hh
rename : base/hybrid_pred.cc => src/base/hybrid_pred.cc
rename : base/hybrid_pred.hh => src/base/hybrid_pred.hh
rename : base/inet.cc => src/base/inet.cc
rename : base/inet.hh => src/base/inet.hh
rename : base/inifile.cc => src/base/inifile.cc
rename : base/inifile.hh => src/base/inifile.hh
rename : base/intmath.cc => src/base/intmath.cc
rename : base/intmath.hh => src/base/intmath.hh
rename : base/kgdb.h => src/base/kgdb.h
rename : base/loader/aout_object.cc => src/base/loader/aout_object.cc
rename : base/loader/aout_object.hh => src/base/loader/aout_object.hh
rename : base/loader/coff_sym.h => src/base/loader/coff_sym.h
rename : base/loader/coff_symconst.h => src/base/loader/coff_symconst.h
rename : base/loader/ecoff_object.cc => src/base/loader/ecoff_object.cc
rename : base/loader/ecoff_object.hh => src/base/loader/ecoff_object.hh
rename : base/loader/elf_object.cc => src/base/loader/elf_object.cc
rename : base/loader/elf_object.hh => src/base/loader/elf_object.hh
rename : base/loader/exec_aout.h => src/base/loader/exec_aout.h
rename : base/loader/exec_ecoff.h => src/base/loader/exec_ecoff.h
rename : base/loader/object_file.cc => src/base/loader/object_file.cc
rename : base/loader/object_file.hh => src/base/loader/object_file.hh
rename : base/loader/symtab.cc => src/base/loader/symtab.cc
rename : base/loader/symtab.hh => src/base/loader/symtab.hh
rename : base/match.cc => src/base/match.cc
rename : base/match.hh => src/base/match.hh
rename : base/misc.cc => src/base/misc.cc
rename : base/misc.hh => src/base/misc.hh
rename : base/mod_num.hh => src/base/mod_num.hh
rename : base/mysql.cc => src/base/mysql.cc
rename : base/mysql.hh => src/base/mysql.hh
rename : base/output.cc => src/base/output.cc
rename : base/output.hh => src/base/output.hh
rename : base/pollevent.cc => src/base/pollevent.cc
rename : base/pollevent.hh => src/base/pollevent.hh
rename : base/predictor.hh => src/base/predictor.hh
rename : base/random.cc => src/base/random.cc
rename : base/random.hh => src/base/random.hh
rename : base/range.cc => src/base/range.cc
rename : base/range.hh => src/base/range.hh
rename : base/refcnt.hh => src/base/refcnt.hh
rename : base/remote_gdb.cc => src/base/remote_gdb.cc
rename : base/remote_gdb.hh => src/base/remote_gdb.hh
rename : base/res_list.hh => src/base/res_list.hh
rename : base/sat_counter.cc => src/base/sat_counter.cc
rename : base/sat_counter.hh => src/base/sat_counter.hh
rename : base/sched_list.hh => src/base/sched_list.hh
rename : base/socket.cc => src/base/socket.cc
rename : base/socket.hh => src/base/socket.hh
rename : base/statistics.cc => src/base/statistics.cc
rename : base/statistics.hh => src/base/statistics.hh
rename : base/stats/events.cc => src/base/stats/events.cc
rename : base/stats/events.hh => src/base/stats/events.hh
rename : base/stats/flags.hh => src/base/stats/flags.hh
rename : base/stats/mysql.cc => src/base/stats/mysql.cc
rename : base/stats/mysql.hh => src/base/stats/mysql.hh
rename : base/stats/mysql_run.hh => src/base/stats/mysql_run.hh
rename : base/stats/output.hh => src/base/stats/output.hh
rename : base/stats/statdb.cc => src/base/stats/statdb.cc
rename : base/stats/statdb.hh => src/base/stats/statdb.hh
rename : base/stats/text.cc => src/base/stats/text.cc
rename : base/stats/text.hh => src/base/stats/text.hh
rename : base/stats/types.hh => src/base/stats/types.hh
rename : base/stats/visit.cc => src/base/stats/visit.cc
rename : base/stats/visit.hh => src/base/stats/visit.hh
rename : base/str.cc => src/base/str.cc
rename : base/str.hh => src/base/str.hh
rename : base/time.cc => src/base/time.cc
rename : base/time.hh => src/base/time.hh
rename : base/timebuf.hh => src/base/timebuf.hh
rename : base/trace.cc => src/base/trace.cc
rename : base/trace.hh => src/base/trace.hh
rename : base/traceflags.py => src/base/traceflags.py
rename : base/userinfo.cc => src/base/userinfo.cc
rename : base/userinfo.hh => src/base/userinfo.hh
rename : cpu/SConscript => src/cpu/SConscript
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst.cc
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/cpu_exec_context.cc => src/cpu/cpu_exec_context.cc
rename : cpu/cpu_exec_context.hh => src/cpu/cpu_exec_context.hh
rename : cpu/cpu_models.py => src/cpu/cpu_models.py
rename : cpu/exec_context.hh => src/cpu/exec_context.hh
rename : cpu/exetrace.cc => src/cpu/exetrace.cc
rename : cpu/exetrace.hh => src/cpu/exetrace.hh
rename : cpu/inst_seq.hh => src/cpu/inst_seq.hh
rename : cpu/intr_control.cc => src/cpu/intr_control.cc
rename : cpu/intr_control.hh => src/cpu/intr_control.hh
rename : cpu/memtest/memtest.cc => src/cpu/memtest/memtest.cc
rename : cpu/memtest/memtest.hh => src/cpu/memtest/memtest.hh
rename : cpu/o3/2bit_local_pred.cc => src/cpu/o3/2bit_local_pred.cc
rename : cpu/o3/2bit_local_pred.hh => src/cpu/o3/2bit_local_pred.hh
rename : cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha_cpu.cc
rename : cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha_cpu.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha_cpu_builder.cc
rename : cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha_cpu_impl.hh
rename : cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha_dyn_inst.cc
rename : cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha_dyn_inst.hh
rename : cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/o3/alpha_impl.hh => src/cpu/o3/alpha_impl.hh
rename : cpu/o3/alpha_params.hh => src/cpu/o3/alpha_params.hh
rename : cpu/o3/bpred_unit.cc => src/cpu/o3/bpred_unit.cc
rename : cpu/o3/bpred_unit.hh => src/cpu/o3/bpred_unit.hh
rename : cpu/o3/bpred_unit_impl.hh => src/cpu/o3/bpred_unit_impl.hh
rename : cpu/o3/btb.cc => src/cpu/o3/btb.cc
rename : cpu/o3/btb.hh => src/cpu/o3/btb.hh
rename : cpu/o3/comm.hh => src/cpu/o3/comm.hh
rename : cpu/o3/commit.cc => src/cpu/o3/commit.cc
rename : cpu/o3/commit.hh => src/cpu/o3/commit.hh
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/cpu.hh => src/cpu/o3/cpu.hh
rename : cpu/o3/cpu_policy.hh => src/cpu/o3/cpu_policy.hh
rename : cpu/o3/decode.cc => src/cpu/o3/decode.cc
rename : cpu/o3/decode.hh => src/cpu/o3/decode.hh
rename : cpu/o3/decode_impl.hh => src/cpu/o3/decode_impl.hh
rename : cpu/o3/fetch.cc => src/cpu/o3/fetch.cc
rename : cpu/o3/fetch.hh => src/cpu/o3/fetch.hh
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/free_list.cc => src/cpu/o3/free_list.cc
rename : cpu/o3/free_list.hh => src/cpu/o3/free_list.hh
rename : cpu/o3/iew.cc => src/cpu/o3/iew.cc
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.cc => src/cpu/o3/inst_queue.cc
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/mem_dep_unit.cc => src/cpu/o3/mem_dep_unit.cc
rename : cpu/o3/mem_dep_unit.hh => src/cpu/o3/mem_dep_unit.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/ras.cc => src/cpu/o3/ras.cc
rename : cpu/o3/ras.hh => src/cpu/o3/ras.hh
rename : cpu/o3/regfile.hh => src/cpu/o3/regfile.hh
rename : cpu/o3/rename.cc => src/cpu/o3/rename.cc
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/rename_map.cc => src/cpu/o3/rename_map.cc
rename : cpu/o3/rename_map.hh => src/cpu/o3/rename_map.hh
rename : cpu/o3/rob.cc => src/cpu/o3/rob.cc
rename : cpu/o3/rob.hh => src/cpu/o3/rob.hh
rename : cpu/o3/rob_impl.hh => src/cpu/o3/rob_impl.hh
rename : cpu/o3/sat_counter.cc => src/cpu/o3/sat_counter.cc
rename : cpu/o3/sat_counter.hh => src/cpu/o3/sat_counter.hh
rename : cpu/o3/store_set.cc => src/cpu/o3/store_set.cc
rename : cpu/o3/store_set.hh => src/cpu/o3/store_set.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/op_class.cc => src/cpu/op_class.cc
rename : cpu/op_class.hh => src/cpu/op_class.hh
rename : cpu/ozone/cpu.cc => src/cpu/ozone/cpu.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/ozone/ea_list.cc => src/cpu/ozone/ea_list.cc
rename : cpu/ozone/ea_list.hh => src/cpu/ozone/ea_list.hh
rename : cpu/pc_event.cc => src/cpu/pc_event.cc
rename : cpu/pc_event.hh => src/cpu/pc_event.hh
rename : cpu/profile.cc => src/cpu/profile.cc
rename : cpu/profile.hh => src/cpu/profile.hh
rename : cpu/simple/atomic.cc => src/cpu/simple/atomic.cc
rename : cpu/simple/atomic.hh => src/cpu/simple/atomic.hh
rename : cpu/simple/base.cc => src/cpu/simple/base.cc
rename : cpu/simple/base.hh => src/cpu/simple/base.hh
rename : cpu/simple/timing.cc => src/cpu/simple/timing.cc
rename : cpu/simple/timing.hh => src/cpu/simple/timing.hh
rename : cpu/smt.hh => src/cpu/smt.hh
rename : cpu/static_inst.cc => src/cpu/static_inst.cc
rename : cpu/static_inst.hh => src/cpu/static_inst.hh
rename : cpu/trace/opt_cpu.cc => src/cpu/trace/opt_cpu.cc
rename : cpu/trace/opt_cpu.hh => src/cpu/trace/opt_cpu.hh
rename : cpu/trace/reader/ibm_reader.cc => src/cpu/trace/reader/ibm_reader.cc
rename : cpu/trace/reader/ibm_reader.hh => src/cpu/trace/reader/ibm_reader.hh
rename : cpu/trace/reader/itx_reader.cc => src/cpu/trace/reader/itx_reader.cc
rename : cpu/trace/reader/itx_reader.hh => src/cpu/trace/reader/itx_reader.hh
rename : cpu/trace/reader/m5_reader.cc => src/cpu/trace/reader/m5_reader.cc
rename : cpu/trace/reader/m5_reader.hh => src/cpu/trace/reader/m5_reader.hh
rename : cpu/trace/reader/mem_trace_reader.cc => src/cpu/trace/reader/mem_trace_reader.cc
rename : cpu/trace/reader/mem_trace_reader.hh => src/cpu/trace/reader/mem_trace_reader.hh
rename : cpu/trace/trace_cpu.cc => src/cpu/trace/trace_cpu.cc
rename : cpu/trace/trace_cpu.hh => src/cpu/trace/trace_cpu.hh
rename : dev/alpha_access.h => src/dev/alpha_access.h
rename : dev/alpha_console.cc => src/dev/alpha_console.cc
rename : dev/alpha_console.hh => src/dev/alpha_console.hh
rename : dev/baddev.cc => src/dev/baddev.cc
rename : dev/baddev.hh => src/dev/baddev.hh
rename : dev/disk_image.cc => src/dev/disk_image.cc
rename : dev/disk_image.hh => src/dev/disk_image.hh
rename : dev/etherbus.cc => src/dev/etherbus.cc
rename : dev/etherbus.hh => src/dev/etherbus.hh
rename : dev/etherdump.cc => src/dev/etherdump.cc
rename : dev/etherdump.hh => src/dev/etherdump.hh
rename : dev/etherint.cc => src/dev/etherint.cc
rename : dev/etherint.hh => src/dev/etherint.hh
rename : dev/etherlink.cc => src/dev/etherlink.cc
rename : dev/etherlink.hh => src/dev/etherlink.hh
rename : dev/etherpkt.cc => src/dev/etherpkt.cc
rename : dev/etherpkt.hh => src/dev/etherpkt.hh
rename : dev/ethertap.cc => src/dev/ethertap.cc
rename : dev/ethertap.hh => src/dev/ethertap.hh
rename : dev/ide_atareg.h => src/dev/ide_atareg.h
rename : dev/ide_ctrl.cc => src/dev/ide_ctrl.cc
rename : dev/ide_ctrl.hh => src/dev/ide_ctrl.hh
rename : dev/ide_disk.cc => src/dev/ide_disk.cc
rename : dev/ide_disk.hh => src/dev/ide_disk.hh
rename : dev/ide_wdcreg.h => src/dev/ide_wdcreg.h
rename : dev/io_device.cc => src/dev/io_device.cc
rename : dev/io_device.hh => src/dev/io_device.hh
rename : dev/isa_fake.cc => src/dev/isa_fake.cc
rename : dev/isa_fake.hh => src/dev/isa_fake.hh
rename : dev/ns_gige.cc => src/dev/ns_gige.cc
rename : dev/ns_gige.hh => src/dev/ns_gige.hh
rename : dev/ns_gige_reg.h => src/dev/ns_gige_reg.h
rename : dev/pciconfigall.cc => src/dev/pciconfigall.cc
rename : dev/pciconfigall.hh => src/dev/pciconfigall.hh
rename : dev/pcidev.cc => src/dev/pcidev.cc
rename : dev/pcidev.hh => src/dev/pcidev.hh
rename : dev/pcireg.h => src/dev/pcireg.h
rename : dev/pitreg.h => src/dev/pitreg.h
rename : dev/pktfifo.cc => src/dev/pktfifo.cc
rename : dev/pktfifo.hh => src/dev/pktfifo.hh
rename : dev/platform.cc => src/dev/platform.cc
rename : dev/platform.hh => src/dev/platform.hh
rename : dev/rtcreg.h => src/dev/rtcreg.h
rename : dev/simconsole.cc => src/dev/simconsole.cc
rename : dev/simconsole.hh => src/dev/simconsole.hh
rename : dev/simple_disk.cc => src/dev/simple_disk.cc
rename : dev/simple_disk.hh => src/dev/simple_disk.hh
rename : dev/sinic.cc => src/dev/sinic.cc
rename : dev/sinic.hh => src/dev/sinic.hh
rename : dev/sinicreg.hh => src/dev/sinicreg.hh
rename : dev/tsunami.cc => src/dev/tsunami.cc
rename : dev/tsunami.hh => src/dev/tsunami.hh
rename : dev/tsunami_cchip.cc => src/dev/tsunami_cchip.cc
rename : dev/tsunami_cchip.hh => src/dev/tsunami_cchip.hh
rename : dev/tsunami_io.cc => src/dev/tsunami_io.cc
rename : dev/tsunami_io.hh => src/dev/tsunami_io.hh
rename : dev/tsunami_pchip.cc => src/dev/tsunami_pchip.cc
rename : dev/tsunami_pchip.hh => src/dev/tsunami_pchip.hh
rename : dev/tsunamireg.h => src/dev/tsunamireg.h
rename : dev/uart.cc => src/dev/uart.cc
rename : dev/uart.hh => src/dev/uart.hh
rename : dev/uart8250.cc => src/dev/uart8250.cc
rename : dev/uart8250.hh => src/dev/uart8250.hh
rename : kern/kernel_stats.cc => src/kern/kernel_stats.cc
rename : kern/kernel_stats.hh => src/kern/kernel_stats.hh
rename : kern/linux/events.cc => src/kern/linux/events.cc
rename : kern/linux/events.hh => src/kern/linux/events.hh
rename : kern/linux/linux.hh => src/kern/linux/linux.hh
rename : kern/linux/linux_syscalls.cc => src/kern/linux/linux_syscalls.cc
rename : kern/linux/linux_syscalls.hh => src/kern/linux/linux_syscalls.hh
rename : kern/linux/printk.cc => src/kern/linux/printk.cc
rename : kern/linux/printk.hh => src/kern/linux/printk.hh
rename : kern/linux/sched.hh => src/kern/linux/sched.hh
rename : kern/solaris/solaris.hh => src/kern/solaris/solaris.hh
rename : kern/system_events.cc => src/kern/system_events.cc
rename : kern/system_events.hh => src/kern/system_events.hh
rename : kern/tru64/dump_mbuf.cc => src/kern/tru64/dump_mbuf.cc
rename : kern/tru64/dump_mbuf.hh => src/kern/tru64/dump_mbuf.hh
rename : kern/tru64/mbuf.hh => src/kern/tru64/mbuf.hh
rename : kern/tru64/printf.cc => src/kern/tru64/printf.cc
rename : kern/tru64/printf.hh => src/kern/tru64/printf.hh
rename : kern/tru64/tru64.hh => src/kern/tru64/tru64.hh
rename : kern/tru64/tru64_events.cc => src/kern/tru64/tru64_events.cc
rename : kern/tru64/tru64_events.hh => src/kern/tru64/tru64_events.hh
rename : kern/tru64/tru64_syscalls.cc => src/kern/tru64/tru64_syscalls.cc
rename : kern/tru64/tru64_syscalls.hh => src/kern/tru64/tru64_syscalls.hh
rename : mem/bridge.cc => src/mem/bridge.cc
rename : mem/bridge.hh => src/mem/bridge.hh
rename : mem/bus.cc => src/mem/bus.cc
rename : mem/bus.hh => src/mem/bus.hh
rename : mem/cache/prefetch/tagged_prefetcher_impl.hh => src/mem/cache/prefetch/tagged_prefetcher_impl.hh
rename : mem/config/prefetch.hh => src/mem/config/prefetch.hh
rename : mem/mem_object.cc => src/mem/mem_object.cc
rename : mem/mem_object.hh => src/mem/mem_object.hh
rename : mem/packet.cc => src/mem/packet.cc
rename : mem/packet.hh => src/mem/packet.hh
rename : mem/page_table.cc => src/mem/page_table.cc
rename : mem/page_table.hh => src/mem/page_table.hh
rename : mem/physical.cc => src/mem/physical.cc
rename : mem/physical.hh => src/mem/physical.hh
rename : mem/port.cc => src/mem/port.cc
rename : mem/port.hh => src/mem/port.hh
rename : mem/request.hh => src/mem/request.hh
rename : mem/translating_port.cc => src/mem/translating_port.cc
rename : mem/translating_port.hh => src/mem/translating_port.hh
rename : mem/vport.cc => src/mem/vport.cc
rename : mem/vport.hh => src/mem/vport.hh
rename : python/SConscript => src/python/SConscript
rename : python/m5/__init__.py => src/python/m5/__init__.py
rename : python/m5/config.py => src/python/m5/config.py
rename : python/m5/convert.py => src/python/m5/convert.py
rename : python/m5/multidict.py => src/python/m5/multidict.py
rename : python/m5/objects/AlphaConsole.py => src/python/m5/objects/AlphaConsole.py
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaFullCPU.py
rename : python/m5/objects/AlphaTLB.py => src/python/m5/objects/AlphaTLB.py
rename : python/m5/objects/BadDevice.py => src/python/m5/objects/BadDevice.py
rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py
rename : python/m5/objects/BaseCache.py => src/python/m5/objects/BaseCache.py
rename : python/m5/objects/Bridge.py => src/python/m5/objects/Bridge.py
rename : python/m5/objects/Bus.py => src/python/m5/objects/Bus.py
rename : python/m5/objects/CoherenceProtocol.py => src/python/m5/objects/CoherenceProtocol.py
rename : python/m5/objects/Device.py => src/python/m5/objects/Device.py
rename : python/m5/objects/DiskImage.py => src/python/m5/objects/DiskImage.py
rename : python/m5/objects/Ethernet.py => src/python/m5/objects/Ethernet.py
rename : python/m5/objects/Ide.py => src/python/m5/objects/Ide.py
rename : python/m5/objects/IntrControl.py => src/python/m5/objects/IntrControl.py
rename : python/m5/objects/MemObject.py => src/python/m5/objects/MemObject.py
rename : python/m5/objects/MemTest.py => src/python/m5/objects/MemTest.py
rename : python/m5/objects/Pci.py => src/python/m5/objects/Pci.py
rename : python/m5/objects/PhysicalMemory.py => src/python/m5/objects/PhysicalMemory.py
rename : python/m5/objects/Platform.py => src/python/m5/objects/Platform.py
rename : python/m5/objects/Process.py => src/python/m5/objects/Process.py
rename : python/m5/objects/Repl.py => src/python/m5/objects/Repl.py
rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py
rename : python/m5/objects/SimConsole.py => src/python/m5/objects/SimConsole.py
rename : python/m5/objects/SimpleDisk.py => src/python/m5/objects/SimpleDisk.py
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : python/m5/objects/Tsunami.py => src/python/m5/objects/Tsunami.py
rename : python/m5/objects/Uart.py => src/python/m5/objects/Uart.py
rename : python/m5/smartdict.py => src/python/m5/smartdict.py
rename : sim/async.hh => src/sim/async.hh
rename : sim/builder.cc => src/sim/builder.cc
rename : sim/builder.hh => src/sim/builder.hh
rename : sim/byteswap.hh => src/sim/byteswap.hh
rename : sim/debug.cc => src/sim/debug.cc
rename : sim/debug.hh => src/sim/debug.hh
rename : sim/eventq.cc => src/sim/eventq.cc
rename : sim/eventq.hh => src/sim/eventq.hh
rename : sim/faults.cc => src/sim/faults.cc
rename : sim/faults.hh => src/sim/faults.hh
rename : sim/host.hh => src/sim/host.hh
rename : sim/main.cc => src/sim/main.cc
rename : sim/param.cc => src/sim/param.cc
rename : sim/param.hh => src/sim/param.hh
rename : sim/process.cc => src/sim/process.cc
rename : sim/process.hh => src/sim/process.hh
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh
rename : sim/root.cc => src/sim/root.cc
rename : sim/serialize.cc => src/sim/serialize.cc
rename : sim/serialize.hh => src/sim/serialize.hh
rename : sim/sim_events.cc => src/sim/sim_events.cc
rename : sim/sim_events.hh => src/sim/sim_events.hh
rename : sim/sim_exit.hh => src/sim/sim_exit.hh
rename : sim/sim_object.cc => src/sim/sim_object.cc
rename : sim/sim_object.hh => src/sim/sim_object.hh
rename : sim/startup.cc => src/sim/startup.cc
rename : sim/startup.hh => src/sim/startup.hh
rename : sim/stat_control.cc => src/sim/stat_control.cc
rename : sim/stat_control.hh => src/sim/stat_control.hh
rename : sim/stats.hh => src/sim/stats.hh
rename : sim/syscall_emul.cc => src/sim/syscall_emul.cc
rename : sim/syscall_emul.hh => src/sim/syscall_emul.hh
rename : sim/system.cc => src/sim/system.cc
rename : sim/system.hh => src/sim/system.hh
rename : sim/vptr.hh => src/sim/vptr.hh
rename : test/Makefile => src/unittest/Makefile
rename : test/bitvectest.cc => src/unittest/bitvectest.cc
rename : test/circletest.cc => src/unittest/circletest.cc
rename : test/cprintftest.cc => src/unittest/cprintftest.cc
rename : test/foo.ini => src/unittest/foo.ini
rename : test/genini.py => src/unittest/genini.py
rename : test/initest.cc => src/unittest/initest.cc
rename : test/initest.ini => src/unittest/initest.ini
rename : test/lru_test.cc => src/unittest/lru_test.cc
rename : test/nmtest.cc => src/unittest/nmtest.cc
rename : test/offtest.cc => src/unittest/offtest.cc
rename : test/paramtest.cc => src/unittest/paramtest.cc
rename : test/rangetest.cc => src/unittest/rangetest.cc
rename : test/sized_test.cc => src/unittest/sized_test.cc
rename : test/stattest.cc => src/unittest/stattest.cc
rename : test/strnumtest.cc => src/unittest/strnumtest.cc
rename : test/symtest.cc => src/unittest/symtest.cc
rename : test/tokentest.cc => src/unittest/tokentest.cc
rename : test/tracetest.cc => src/unittest/tracetest.cc
extra : convert_revision :
cab6a5271ca1b368193cd948e5d3dcc47ab1bd48
Kevin Lim [Sun, 21 May 2006 05:55:58 +0000 (01:55 -0400)]
Threads start off in suspended status now (Korey's changes for SMT).
--HG--
extra : convert_revision :
ad726f9f258e1983d2af5057ff6e5f9d2a5dd072
Kevin Lim [Fri, 19 May 2006 19:53:17 +0000 (15:53 -0400)]
O3 code update/cleanup.
cpu/o3/commit_impl.hh:
O3 code update/cleanup. Fetch fault code no longer needed (see previous checkin).
--HG--
extra : convert_revision :
f602e7f978e19b8900dce482f38f9c7a195e94da
Kevin Lim [Fri, 19 May 2006 19:47:55 +0000 (15:47 -0400)]
Remove sat_counter.cc and put its code into sat_counter.hh.
cpu/SConscript:
Remove sat_counter.cc and push its functions into the .hh file (all functions were 3 or less lines).
cpu/o3/sat_counter.hh:
Incorporate .cc code into this file.
--HG--
extra : convert_revision :
d75b1319292b00b00af1ce377cc0215fd06e6916
Kevin Lim [Fri, 19 May 2006 19:45:06 +0000 (15:45 -0400)]
Rename function to be more expressive.
--HG--
extra : convert_revision :
0c01b6d5309e2d09f03631740c9b0c8619ea26c4
Kevin Lim [Fri, 19 May 2006 19:44:03 +0000 (15:44 -0400)]
IEW/IQ code cleanup and reorganization.
Dependecy graph code moved into its own class.
This requires the changes to the functional units, which is in the next check in.
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
IEW and IQ code cleanup and reorganization.
cpu/o3/inst_queue.cc:
Dependency graph code moved into its own class now.
cpu/o3/inst_queue.hh:
IEW/IQ code cleanup and reorganization.
Dependecy graph code moved into its own class.
cpu/o3/inst_queue_impl.hh:
IEW/IQ code cleanup and reorganization.
Dependecy graph code moved into its own class.
Issue loop cleaned up, with completion events for functional units now used more correctly (before they weren't used for multi-cycle ops with pipelined FU's).
--HG--
extra : convert_revision :
35e50192df6f71dc81d46a73fdd65f7ec07c10e4
Kevin Lim [Fri, 19 May 2006 19:37:52 +0000 (15:37 -0400)]
Move activity tracking code into its own class. Now the CPU no longer has to keep track of the activity tracking internals; it just calls advance() on the class and uses it to tell if it should deschedule itself.
SConscript:
Split off activity/idling code into its own class to do the processing separately.
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_params.hh:
Activity stuff. This is mostly for debugging and may be removed later on (or changed to enable/disable activity idling).
cpu/o3/cpu.cc:
Move activity idling stuff mostly into its own class, so it no longer clutters this file.
cpu/o3/cpu.hh:
Move activity idling stuff into its own class.
python/m5/objects/AlphaFullCPU.py:
Add parameter for initial activity value.
--HG--
extra : convert_revision :
f32f7cc03895dc07ab57ddba78c5402a1a8b0f1a
Kevin Lim [Fri, 19 May 2006 18:27:46 +0000 (14:27 -0400)]
Fixes for regression build errors.
--HG--
extra : convert_revision :
1f59c853cb0e327d7cf586021b5139f1242e4f28
Steve Reinhardt [Fri, 19 May 2006 02:54:19 +0000 (22:54 -0400)]
First steps toward getting full system to work with
TimingSimpleCPU. Not there yet.
cpu/simple/atomic.cc:
Only read SC result if store was an SC.
Don't fake SC here; fake it in PhysicalMemory so
all CPU models can share in the joy.
cpu/simple/timing.cc:
Don't forget to checkForInterrupts().
Only fetch subsequent instruction if we're still running
(i.e. not quiesced).
dev/io_device.hh:
Initialize port pointer in SendEvent object.
mem/physical.cc:
Move fake SC "implementation" here from AtomicSimpleCPU.
mem/request.hh:
Initialize flags to all clear, not uninitialized.
Otherwise we can't reliably look at flags w/o explicitly
setting them every time we create a request.
--HG--
extra : convert_revision :
ae7601ce6fb54c54e19848aa5391327f9a6e61a6
Steve Reinhardt [Fri, 19 May 2006 02:32:21 +0000 (22:32 -0400)]
Change Packet parameters on Port methods from references to pointers.
--HG--
extra : convert_revision :
7193e70304d4cbe1e4cbe16ce0d8527b2754d066
Ali Saidi [Thu, 18 May 2006 17:33:14 +0000 (13:33 -0400)]
add regStats() back to ide_disk
add sinic back to sconscript file
SConscript:
add sinic back to sconscript file
dev/ide_disk.hh:
add regStats() back to ide_disk
--HG--
extra : convert_revision :
a25083993190ceadde977283fbd1fb64e8e7ef86
Ali Saidi [Thu, 18 May 2006 16:52:37 +0000 (12:52 -0400)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.nm_m5_pull
--HG--
extra : convert_revision :
f7ceb689dc5594c746e22a27d6061a767daba261
Ali Saidi [Thu, 18 May 2006 16:52:16 +0000 (12:52 -0400)]
fix ide stats and make sinic compile after merge.
dev/ide_disk.cc:
fix dma stats
dev/sinic.cc:
make sinic compile
--HG--
extra : convert_revision :
fbea04ca58f6ab52e98108f7c2b12917c2fe22d6
Steve Reinhardt [Thu, 18 May 2006 02:08:44 +0000 (22:08 -0400)]
Get basic full-system working with AtomicSimpleCPU.
SConscript:
Comment out sinic for now... needs to be fixed to compile under newmem.
configs/test/SysPaths.py:
Fix paths.
configs/test/fs.py:
SimpleCPU -> AtomicSimpleCPU
Fix vmlinux path
cpu/simple/atomic.cc:
Fix suspendContext() so quiesce works.
Don't forget to checkForInterrupts().
cpu/simple/base.cc:
Minor fix to interrupt check code.
dev/ide_disk.hh:
Don't declare regStats() in header since it's not in
.cc file anymore (will need to add it back in when
stats are added back).
dev/io_device.cc:
Set packet dest to Packet::Broadcast.
dev/pciconfigall.cc:
Set PCI config packet result to Success.
python/m5/objects/Root.py:
Add debug object to Root so things like break_cycles
can be set from command line.
--HG--
extra : convert_revision :
aa1c652fe589784e753e13ad9acb0cd5f3b6eafb
Kevin Lim [Wed, 17 May 2006 18:25:10 +0000 (14:25 -0400)]
Faults generated at fetch are passed to the backend by creating a dummy nop instruction and giving it the fault. This unifies front end faults and normal instruction faults.
cpu/checker/cpu.cc:
Fixups for fetch fault being sent with the instruction.
cpu/o3/fetch_impl.hh:
cpu/ozone/front_end_impl.hh:
Send any faults generated at fetch along with a fake nop instruction to the back end. This avoids having to use direct communication to check if the entire front end has drained; it is naturally handled through the nop's fault being handled when it reaches the head of commit.
cpu/ozone/front_end.hh:
Add extra status TrapPending.
cpu/ozone/lw_back_end_impl.hh:
Fetch fault handled through a dummy nop carrying the fetch fault.
Avoid putting Nops on the exeList.
--HG--
extra : convert_revision :
8d9899748b34c204763a49c48a9b5113864f5789
Steve Reinhardt [Wed, 17 May 2006 11:05:27 +0000 (07:05 -0400)]
Backport ISA scanner fix from newmem to work with
scons 0.96.9* versions.
arch/SConscript:
Backport ISA scanner fix from newmem.
--HG--
extra : convert_revision :
96be75660f85900fd26badef36fb4109b36d8394
Ali Saidi [Wed, 17 May 2006 03:58:37 +0000 (23:58 -0400)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
efa962c4ea614e22e8964f6979cd7c9dcd4ee866
Ali Saidi [Wed, 17 May 2006 03:58:31 +0000 (23:58 -0400)]
add single fs newmem test
--HG--
extra : convert_revision :
895beeae44a36f585656e33a4a403dbedbe694ea
Steve Reinhardt [Tue, 16 May 2006 21:36:50 +0000 (17:36 -0400)]
Split SimpleCPU into two different models, AtomicSimpleCPU and
TimingSimpleCPU, which use atomic and timing memory accesses
respectively. Common code is factored into the BaseSimpleCPU class.
AtomicSimpleCPU includes an option (simulate_stalls) to add delays
based on the estimated latency reported by the atomic accesses.
Plain old "SimpleCPU" is gone; I have not updated all the config
files (just test/test.py).
Also fixes to get timing accesses working in new memory model and
to get split-phase memory instruction definitions working with
new memory model as well.
arch/alpha/isa/main.isa:
Need to include packet_impl.h for functions that use Packet objects.
arch/alpha/isa/mem.isa:
Change completeAcc() methods to take Packet object pointers.
Also split out StoreCond template for completeAcc(), since
that's the only one that needs write_result and we get an
unused variable warning if we always have it in there.
build/SConstruct:
Update list of recognized CPU model names.
configs/test/test.py:
Change SimpleCPU to AtomicSimpleCPU.
cpu/SConscript:
Define sources for new CPU models.
Add split memory access methods to CPU model signatures.
cpu/cpu_models.py:
cpu/static_inst.hh:
Define new CPU models.
cpu/simple/base.cc:
cpu/simple/base.hh:
Factor out pieces specific to Atomic or Timing models.
mem/bus.cc:
Bus needs to be able to route timing packets based on explicit dest
so responses can get back to requester. Set dest to Packet::Broadcast
to indicate that dest should be derived from address.
Also set packet src field based on port from which packet is sent.
mem/bus.hh:
Set packet src field based on port from which packet is sent.
mem/packet.hh:
Define Broadcast destination address to indicate that
packet should be routed based on address.
mem/physical.cc:
Set packet dest on response so packet is routed
back to requester properly.
mem/port.cc:
Flag blob packets as Broadcast.
python/m5/objects/PhysicalMemory.py:
Change default latency to be 1 cycle.
--HG--
rename : cpu/simple/cpu.cc => cpu/simple/base.cc
rename : cpu/simple/cpu.hh => cpu/simple/base.hh
extra : convert_revision :
e9646af6406a20c8c605087936dc4683375c2132
Kevin Lim [Tue, 16 May 2006 19:30:36 +0000 (15:30 -0400)]
Merge ktlim@zamp:/z/ktlim2/clean/m5-o3
into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-merge
--HG--
extra : convert_revision :
077a04edf0e3e4d735e88c9741d6742666e97de6
Kevin Lim [Tue, 16 May 2006 19:25:46 +0000 (15:25 -0400)]
Update configuration files.
--HG--
extra : convert_revision :
f733bc68758d95987dfc481d48a4623c23b16ede
Kevin Lim [Tue, 16 May 2006 19:09:06 +0000 (15:09 -0400)]
Merge ktlim@zizzer:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-merge
--HG--
extra : convert_revision :
182df443376e5561d46f323d36089a2a49dc2024
Kevin Lim [Tue, 16 May 2006 18:47:09 +0000 (14:47 -0400)]
Include checker and trap latency parameters.
--HG--
extra : convert_revision :
148c59f430874e8425952db6960ca4f5e57e2a42
Kevin Lim [Tue, 16 May 2006 18:09:04 +0000 (14:09 -0400)]
Sampler updates.
cpu/ozone/cpu.hh:
Updates for sampler.
cpu/ozone/cpu_impl.hh:
Updates for sampler, checker.
cpu/ozone/inorder_back_end.hh:
Sampler updates. Also support old memory system.
--HG--
extra : convert_revision :
33ebe38e4c08d49c6af84032b819533b784b4fe8
Kevin Lim [Tue, 16 May 2006 18:06:35 +0000 (14:06 -0400)]
Updates for sampler, checker, and general correctness.
cpu/o3/alpha_cpu.hh:
Update for sampler to work properly. Also code cleanup.
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_dyn_inst.hh:
Updates to support the checker.
cpu/o3/alpha_cpu_impl.hh:
Updates to support the checker. Also general code cleanup.
cpu/o3/alpha_dyn_inst_impl.hh:
Code cleanup.
cpu/o3/alpha_params.hh:
Updates to support the checker. Also supports trap latencies set through the parameters.
cpu/o3/commit.hh:
Supports sampler, checker. Code cleanup.
cpu/o3/commit_impl.hh:
Updates to support the sampler and checker, as well as general code cleanup.
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
Support sampler and checker.
cpu/o3/decode_impl.hh:
Supports sampler.
cpu/o3/fetch.hh:
Supports sampler. Also update to hold the youngest valid SN fetch has seen to ensure that the entire pipeline has been drained.
cpu/o3/fetch_impl.hh:
Sampler updates. Also be sure to not fetches to uncached space (bad path).
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
Sampler updates.
cpu/o3/lsq_unit_impl.hh:
Supports checker.
cpu/o3/regfile.hh:
No need for accessing xcProxies directly.
cpu/o3/rename.hh:
cpu/o3/rename_impl.hh:
Sampler support.
--HG--
extra : convert_revision :
03881885dd50ebbca13ef31f31492fd4ef59121c
Kevin Lim [Tue, 16 May 2006 17:59:29 +0000 (13:59 -0400)]
Add in checker. Supports dynamically verifying the execution of instructions, as well as limited amount of control path verification. It will verify anything within the program, but anything external (traps, interrupts, XC) it assumes is redirected properly by the CPU. Similarly it assumes the results of store conditionals, uncached loads, and instructions marked as "unverifiable" are correct from the CPU.
base/traceflags.py:
build/SConstruct:
cpu/SConscript:
cpu/cpu_models.py:
Add in Checker.
cpu/base.cc:
Add in checker support. Also XC status starts off as suspended.
cpu/base.hh:
Add in checker.
--HG--
extra : convert_revision :
091b5cc83e837858adb681ef0137a0beb30bd1b2
Kevin Lim [Tue, 16 May 2006 17:52:03 +0000 (13:52 -0400)]
Sampler updates.
--HG--
extra : convert_revision :
9f88846d3e91ba725e1c2e0107568ba0f21f4638
Kevin Lim [Tue, 16 May 2006 17:51:18 +0000 (13:51 -0400)]
Sampling fixes related to the quiesce event.
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
Sampling fixes. The CPU models may switch during a quiesce period, so it needs to be sure to wake up the right XC.
cpu/exec_context.hh:
Return the EndQuiesceEvent specifically.
sim/pseudo_inst.cc:
Return the EndQuiesceEvent specifically for sampling.
--HG--
extra : convert_revision :
f9aa1fc8d4db8058f05319cb6a3d4605ce93b4c8
Kevin Lim [Tue, 16 May 2006 17:48:05 +0000 (13:48 -0400)]
Add some flags for the upcoming checker.
arch/alpha/isa/decoder.isa:
Mark store conditionals as serializing. This is slightly higher over head than they truly have in the 264, but it's close. Normally they block any other instructions from entering the IQ until the IQ is empty. This is higher overhead because it waits until the ROB is empty.
Also mark RPCC as unverifiable. The checker will just grab the value from the instruction and assume it's correct.
cpu/static_inst.hh:
Add unverifiable flag, specifically for the CheckerCPU.
--HG--
extra : convert_revision :
cbc34d1f2f5b07105d31d4bd8f19edae2cf8158e
Steve Reinhardt [Tue, 16 May 2006 00:30:20 +0000 (20:30 -0400)]
Many files:
Get rid of more unneeded includes.
base/hostinfo.cc:
base/inet.cc:
base/remote_gdb.cc:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/disk_image.cc:
dev/ns_gige.cc:
dev/sinic.cc:
mem/physical.cc:
sim/param.cc:
sim/process.cc:
sim/pseudo_inst.cc:
test/cprintftest.cc:
Get rid of more unneeded includes.
--HG--
extra : convert_revision :
f531ae40db3787f2c55df7d251f251ecae4ab731
Steve Reinhardt [Tue, 16 May 2006 00:06:42 +0000 (20:06 -0400)]
Many files:
Fix sstream includes
arch/alpha/tlb.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/crc.cc:
base/statistics.cc:
base/statistics.hh:
base/stats/text.cc:
cpu/memtest/memtest.cc:
cpu/simple/cpu.cc:
dev/pcidev.cc:
sim/eventq.cc:
Fix sstream includes
--HG--
extra : convert_revision :
fd69937ea26b4961e92f1736fa44daa16f54698d
Ali Saidi [Mon, 15 May 2006 21:52:50 +0000 (17:52 -0400)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
base/loader/elf_object.cc:
removed SPARC32PLUS since it doesn't work.
--HG--
extra : convert_revision :
620a1c75cdeefbeeb97383d92335cf319d9c9444
Ali Saidi [Mon, 15 May 2006 21:37:03 +0000 (17:37 -0400)]
Add support for sparc/solaris syscall emulation. Not tested yet because I can't get a static sparc 64 binary
arch/sparc/SConscript:
arch/sparc/process.cc:
base/loader/elf_object.cc:
Add support for sparc/solaris syscall emulation.
--HG--
extra : convert_revision :
e22df8476e5c6ae14db1cab1d94d01c0578ea06c
Ali Saidi [Mon, 15 May 2006 21:35:51 +0000 (17:35 -0400)]
fix typo, headers protection should be named __DIR_DIR_..._FILE_HH__
--HG--
extra : convert_revision :
18268bfcb8575a33659ae94b821e1f4cc9b7d821
Gabe Black [Mon, 15 May 2006 03:58:23 +0000 (23:58 -0400)]
Merge m5.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem
--HG--
extra : convert_revision :
2db5529a9fbe8c62e57cad05f093c915f9713c67
Gabe Black [Mon, 15 May 2006 03:57:21 +0000 (23:57 -0400)]
Fixed some problems with signed vs. unsigned numbers which were breaking conditional moves and signed divisions. Also did some minor clean ups.
--HG--
extra : convert_revision :
6389ec18387a68ea5b675badfe1fd10cd30c264d
Gabe Black [Mon, 15 May 2006 03:56:16 +0000 (23:56 -0400)]
Made the decoder handle reg_or_imm type arguments with type qualifiers.
--HG--
extra : convert_revision :
f0ec58d754401fa6f3d64998355644882c5f5c96
Gabe Black [Mon, 15 May 2006 03:55:07 +0000 (23:55 -0400)]
Made EM_SPARC32PLUS be recognized as belonging to the SPARC architecture. Programs which have this set will not work because the stack works differently, so this should probably throw an error and quit.
--HG--
extra : convert_revision :
b770045cad02d30445de0d7cc4d8c611a0ac931f
Gabe Black [Mon, 15 May 2006 03:53:29 +0000 (23:53 -0400)]
Moved the UnimpFault to be global
--HG--
extra : convert_revision :
a42224c70c475c1559e83b8a2ef71ff3b792a3ab
Gabe Black [Mon, 15 May 2006 03:52:45 +0000 (23:52 -0400)]
Copied Korey's MIPS tests over to SPARC
--HG--
extra : convert_revision :
bcfefd77c35245ce938ecb9bb46e97ad07377db8
Ali Saidi [Fri, 12 May 2006 22:51:42 +0000 (18:51 -0400)]
Merge zeep.pool:/z/saidi/work/m5.head
into zeep.pool:/z/saidi/work/m5.nm_m5_pull
--HG--
extra : convert_revision :
fc90e4e8eefd78a3b7554e06fbc666965794753b
Ali Saidi [Fri, 12 May 2006 22:51:23 +0000 (18:51 -0400)]
replace /.automount/ with /n/
--HG--
extra : convert_revision :
8b9ad49fa7e2e8863ebaf3f6709fc4fda62f2862
Ali Saidi [Fri, 12 May 2006 22:16:07 +0000 (18:16 -0400)]
Merge zeep.pool:/z/saidi/work/m5.head
into zeep.pool:/z/saidi/work/m5.nm_m5_pull
SConscript:
dram memory needs to be converted to newmem before we can use it
dev/ide_ctrl.cc:
don't need this printing in newmem
dev/ide_disk.cc:
will read stats in next commit
dev/sinic.cc:
merge sinic from head, still needs work
--HG--
extra : convert_revision :
b9aabd8c7814d07d54ce6f971aad3ec349fa24e1
Ali Saidi [Fri, 12 May 2006 21:47:23 +0000 (17:47 -0400)]
fix the checkpoint bug
--HG--
extra : convert_revision :
1ccae3282737d70b14ff86c8647e2e662a42c3bc
Korey Sewell [Fri, 12 May 2006 06:57:32 +0000 (02:57 -0400)]
FP programs are back to running... Condition Codes can be read and set...
Special Regs (Hi,Lo,FCSR) are now added to the operands for use in decoder.isa.
Now it's back to just debugging execution of code for the release (those unaligned
memory access instruction pairs are still quite the pain i might add)
arch/mips/isa_traits.hh:
declare functions for .cc file
arch/mips/isa_traits.cc:
delete unnecessary overloaded functions
implement condition code functions
implement round function
arch/mips/isa/base.isa:
remove R31 constant... define in the operands.isa file instead
arch/mips/isa/decoder.isa:
wholesale changes once again to FP.
Now the FP Condition Codes are implemented and the FP programs can
run and complete to finish.
Use isnan() instead of my unorderedFP() function
Also, we now access special regs such as HI,LO,FCSR,etc. just like we do any other reg. operand
arch/mips/isa/operands.isa:
add more operands for special control regs in int and FP regfiles
arch/mips/isa/formats/branch.isa:
use R31 instead of r31
arch/mips/isa/formats/fp.isa:
use MakeCCVector to set Condition Codes in FCSR
arch/mips/regfile/float_regfile.hh:
treat control regs like any other reg. Just Index them after the regular architectural registers
arch/mips/regfile/int_regfile.hh:
treat hi,lo as regular int. regs w/special indexing
arch/mips/regfile/regfile.hh:
no longer need for special register accesses with their own function.
--HG--
rename : arch/mips/regfile.hh => arch/mips/regfile/regfile.hh
extra : convert_revision :
5d2f8fdb59606de2b2e9db3e0a085240561e479e
Kevin Lim [Thu, 11 May 2006 23:18:36 +0000 (19:18 -0400)]
Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision :
f4d408e1bb1f25836a097b6abe3856111e950c59
Ron Dreslinski [Thu, 11 May 2006 21:26:11 +0000 (17:26 -0400)]
Initialize the count on the number of devices drained properly.
--HG--
extra : convert_revision :
80833647202985d1c1c7d23c6896831fcd27ff40
Ron Dreslinski [Thu, 11 May 2006 21:24:15 +0000 (17:24 -0400)]
First pass at a serializer object, may need to work on naming of object and functions:
Intended Use:
A SimObject will call the serializer when it needs the state to be serializable (i.e. switchCPUs, checkpoint, switch memory access model). It will call the requestSeialization() function.
The Serializer will signal all the objects in its list to drain their state via the SimObject method drain(). Drain() has a default implementation to just signal done.
When each object is drained it will signal the Serializer that it has drained via the signalDrained() function.
The Serializer will collect these signals, when all have drained it will signal the initial requestor via serializationComplete() method in the SimObject.
Once that object is done, it will signal the Serializer to resumeExecution().
The Serializer will signal all the objects in its list to resume via the resume() method on the SimObject.
SConscript:
Add serializer object to build list
sim/sim_object.cc:
Add default behavior for drain (just signal finished, must be overided if you really must drain something)
sim/sim_object.hh:
Add functions for serializer
--HG--
extra : convert_revision :
15aa2d1b42010c2d703bef9114c11d079c216170
Ali Saidi [Thu, 11 May 2006 21:19:17 +0000 (17:19 -0400)]
make the dma buffer equal to the max dma size
--HG--
extra : convert_revision :
87adee6c2239f67976675c9291dc4fbaa4f67507
Ali Saidi [Thu, 11 May 2006 21:18:19 +0000 (17:18 -0400)]
ide printing to match newmem
--HG--
extra : convert_revision :
ca6665bd93d257a8cf9d43600828ac22998c5810
Ali Saidi [Thu, 11 May 2006 21:17:47 +0000 (17:17 -0400)]
make m5 panic a little more verbose
--HG--
extra : convert_revision :
32f52d829040c06c8a62cab1a7af1ed3b453b6f9
Kevin Lim [Thu, 11 May 2006 19:39:02 +0000 (15:39 -0400)]
Small fixes to O3 model.
cpu/o3/alpha_dyn_inst.hh:
Set the instResult using a function on the base dyn inst.
cpu/o3/bpred_unit_impl.hh:
Don't need to reset the state.
cpu/o3/commit_impl.hh:
Mark instructions as completed.
Wait until all stores are written back to handle a fault.
cpu/o3/cpu.cc:
Clear instruction lists when switching out.
cpu/o3/lsq_unit.hh:
Allow wbEvent to be set externally.
cpu/o3/lsq_unit_impl.hh:
Mark instructions as completed properly. Also use events for writing back stores even if there is a hit in the dcache.
--HG--
extra : convert_revision :
172ad088b75ac31e848a5040633152b5c051444c
Kevin Lim [Thu, 11 May 2006 19:19:48 +0000 (15:19 -0400)]
Set memory properly.
--HG--
extra : convert_revision :
4e6c61d31bf052bb4aabf4bb7a4f0e870b44b771
Kevin Lim [Thu, 11 May 2006 18:12:34 +0000 (14:12 -0400)]
Separate out result being ready and the instruction being complete.
--HG--
extra : convert_revision :
9f17af114bf639f8fb61896e49fa714932c081d7
Korey Sewell [Thu, 11 May 2006 07:26:19 +0000 (03:26 -0400)]
Fixes for Paired-Single FP Compare Operations...
Now all the variations of FP should be implemented correctly in the decoder.
The new formats and functions supporting these functions need to be implemented for
some of the FP stuff but for the most part things are looking like their "supposed to"...
arch/mips/isa/decoder.isa:
Fixes for Paired-Single FP Compare Operations...
Now all the variations of FP should be implemented correctly in the decoder.
arch/mips/isa/formats/fp.isa:
Add new PS formats
arch/mips/isa_traits.cc:
Add skeleton overloaded round & truncate functions
arch/mips/isa_traits.hh:
declare overloaded functions
--HG--
extra : convert_revision :
15d5cf7b08ac2dc9ebcd6b268e92d4abffdd8597
Korey Sewell [Thu, 11 May 2006 00:54:03 +0000 (20:54 -0400)]
Support for FP Paired Single Operations
Auxiliary Functions and Formats for FP in general
arch/mips/isa/decoder.isa:
ISA Parser doesnt accept operands of different types in one instruction so fix this for unorderedFP functions...
Add basic support for Paired Singled (PS) FP ops which happen to be part of the MIPS 32-ASE but turned out to
be included in the MIPS32ISA manual... The PS instructions allow SIMD in a pipeline...
arch/mips/isa/formats/fp.isa:
Add some more Formats for FP operation. I will add some auxiliary code through these formats
to alleviate code redundancy in the decoder.isa
arch/mips/isa/operands.isa:
Add operands for Paired Singles Ops
arch/mips/isa_traits.cc:
removed convert&round function and replace with fpConvert.
The whole "rounding mode" stuff is something that should be considered for full-system mode...
Also added skeletons for the unorderedFP,truncFP,and condition code funcs.
arch/mips/isa_traits.hh:
declare some Functions
arch/mips/types.hh:
add new conversion types
--HG--
extra : convert_revision :
79251d590a27b74a3d6a62a2fbb937df3e59963f
Korey Sewell [Wed, 10 May 2006 22:34:26 +0000 (18:34 -0400)]
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem
--HG--
extra : convert_revision :
0a146eed200abd2c18f135b112987c5cf91a649b
Korey Sewell [Wed, 10 May 2006 20:52:27 +0000 (16:52 -0400)]
revamping code to appropriately handle FP condition code and conversion ops.
There still needs to be a work around to handle the paired singles operations ...
arch/mips/isa/decoder.isa:
More revamping of the floating point ops in decoder.isa. Change all of the
"convert and round" functions to fpConvert. Also, the utility functions
roundFP, truncFP, and unorderedFP are in place everywhere. Things
have been set up to appropriately use the FP condition codes in the decoder.isa
The fp.isa format file and the isa_traits.cc file now needed to be updated
to implement the appropriate "backend" operations/functionality...
arch/mips/isa_traits.hh:
Remove convert & round functions
Add roundFP, truncFP,unorderedFP, and the get/setFPconditionCode
functions
arch/mips/isa_traits.cc:
Add utility functions
--HG--
extra : convert_revision :
3d6708388abae5b432467f528d52e6343afecd9c
Korey Sewell [Wed, 10 May 2006 12:33:52 +0000 (08:33 -0400)]
decoder.isa:
Now handles instructions for FP compares in single or double recision
arch/mips/isa/decoder.isa:
Now handles instructions for FP compares in single or double recision
--HG--
extra : convert_revision :
eb3a13616e6736bf2d1ead0b816dda8c6099b20f
Korey Sewell [Tue, 9 May 2006 19:18:36 +0000 (15:18 -0400)]
decoder.isa:
Basic Code for Floating Point Compare with Single Precision Floats
Added.
arch/mips/isa/decoder.isa:
Basic Code for Floating Point Compare with Single Precision Floats
Added.
--HG--
extra : convert_revision :
56b14da1e9d987c2d2090fd2f79af8b12fe8d2ec
Korey Sewell [Tue, 9 May 2006 18:39:45 +0000 (14:39 -0400)]
decoder.isa:
Added support for FP compare instructions. Somehow these flew beneath
my radar. Also, I start to use special FP utility functions in FP code.
Right now, they are defined in isa_traits.hh but may be moved in the
future
arch/mips/isa/decoder.isa:
Added support for FP compare instructions. Somehow these flew beneath
my radar. Also, I start to use special FP utility functions in FP code.
Right now, they are defined in isa_traits.hh but may be moved in the
future
--HG--
extra : convert_revision :
84a3b66882f3977ce9c1356cf466d62a7fd8bf19
Steve Reinhardt [Tue, 9 May 2006 16:43:01 +0000 (12:43 -0400)]
Print M5 build options for 'scons -h'.
--HG--
extra : convert_revision :
14ef62e513987b89e913e2bf9b8771ee086ed0a0
Korey Sewell [Mon, 8 May 2006 07:59:40 +0000 (03:59 -0400)]
Start working on more complex FP tests
Debug FP instructions to handle these FP insts
arch/mips/isa/bitfields.isa:
add Bitfield for Floating Point Condition Codes
arch/mips/isa/decoder.isa:
Follow instruction naming style with FP single insts
Send the float value to the convert&round functions in single FP
add ll inst support
add 'token' sc support
arch/mips/isa_traits.cc:
Add SINGLE->WORD, WORD->SINGLE, & WORD->DOUBLE conversions
arch/mips/regfile.hh:
update header files
arch/mips/regfile/float_regfile.hh:
Add more FP registers
--HG--
rename : arch/mips/int_regfile.hh => arch/mips/regfile/int_regfile.hh
rename : arch/mips/misc_regfile.hh => arch/mips/regfile/misc_regfile.hh
extra : convert_revision :
92faf0bfd8542ade762ac569ec158d198f6a9c7e
Korey Sewell [Sun, 7 May 2006 22:50:41 +0000 (18:50 -0400)]
First Steps in cleaning up MIPS code - This changeset rearranges the files in the MIPS directory by moving where constants/types/classes are defined
arch/mips/SConscript:
arch/mips/isa_traits.cc:
arch/mips/isa_traits.hh:
arch/mips/process.cc:
arch/mips/linux/linux.cc:
arch/mips/utility.hh:
arch/mips/linux/process.cc:
arch/mips/int_regfile.hh:
arch/mips/misc_regfile.hh:
arch/mips/regfile.hh:
arch/mips/types.hh:
MIPS directory rearranging
--HG--
rename : arch/mips/mips_linux.cc => arch/mips/linux/linux.cc
rename : arch/mips/mips_linux.hh => arch/mips/linux/linux.hh
rename : arch/mips/linux_process.cc => arch/mips/linux/process.cc
rename : arch/mips/linux_process.hh => arch/mips/linux/process.hh
extra : convert_revision :
138eee48c8ed75efcf38572f335a556aaec38fc7
Korey Sewell [Sun, 7 May 2006 18:09:19 +0000 (14:09 -0400)]
Minor changes for FP ... MIPS now works for floating-point programs...
Now we are to the point where more benchmarks and instruction-coverage
is necessary to totally verify/validate correct operation across
all MIPS instructions
arch/mips/isa_traits.hh:
fix for reading double values ... must rearrange bits before using void* to read double.
configs/test/hello_mips:
real hello world MIPS binary
--HG--
extra : convert_revision :
153de1f8a830882c6972bd0bdb56da818f614def
Korey Sewell [Sun, 7 May 2006 17:26:15 +0000 (13:26 -0400)]
Basic MIPS floating point test works now ... I had to realize that when using the double FP reg the
register with the higher # contains the most significant bytes...
arch/mips/isa/decoder.isa:
divide instruction fixes
arch/mips/isa_traits.cc:
use double as argument to cvt & round function.
clean up cout statements in function.
arch/mips/isa_traits.hh:
In MIPS the higher # reg of a doubles pair is ALSO the most significant reg.
Once I switched this the basic MIPS FP test I had worked.
--HG--
extra : convert_revision :
45c80df229e6174d0b52fc7cfb530642b1f1fc35
projects / gem5.git / log