gem5.git
7 months agotests: arch-power: Add 64-bit hello binaries develop-power develop-gem5-snapshot
Sandipan Das [Sun, 7 Feb 2021 09:33:05 +0000 (09:33 +0000)]
tests: arch-power: Add 64-bit hello binaries

This adds 64-bit statically linked big and little endian
binaries for the hello test program.

It should be noted that all possible combinations of ABI
version and endianness are possible for 64-bit binaries.
However, standard toolchains always use ELF ABI v1 for
big endian and ELF ABI v2 for little endian binaries.

Change-Id: I2dca7eaa2b04a7b68b117ada799d4c3bb69368be
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agotests: arch-power: Move 32-bit hello binary
Sandipan Das [Sat, 6 Feb 2021 14:02:44 +0000 (19:32 +0530)]
tests: arch-power: Move 32-bit hello binary

This moves the 32-bit hello binary for Power under the
linux subdirectory like it was originally before being
removed and reintroduced.

Change-Id: I5f3da38f9abdda90b31755ce7e7c955838cc7289
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agotests: arch-power: Add support for building hello
Sandipan Das [Sat, 6 Feb 2021 13:44:29 +0000 (19:14 +0530)]
tests: arch-power: Add support for building hello

Commit a440108cc ("tests: Add Makefiles for hello")
introduced Makefiles for building the hello test binary
for ARM and x86 using dockcross. Since dockcross also
provides an image with a 64-bit little endian toolchain
for Power, this adds a Makefile for building the hello
binary.

As of this moment, 64-bit little endian (ppc64le) is the
prevalent variant supported by most distributions. Hence,
we are currently limited to only building the binary for
this variant.

Change-Id: Ic20322ca33c69634d9f17d30b29e522cc35742fb
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Update copyrights
Sandipan Das [Sat, 6 Feb 2021 12:21:30 +0000 (17:51 +0530)]
arch-power: Update copyrights

Change-Id: Ifabd1e7178b5250767a2b560b57570512b732278
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Fix load-store instructions for timing cpu
Sandipan Das [Sat, 6 Feb 2021 12:21:07 +0000 (17:51 +0530)]
arch-power: Fix load-store instructions for timing cpu

To properly implement load-store instructions for use with
the TimingSimpleCPU model, the initiateAcc() part of the
instruction should only be responsible for performing the
effective address computation and then initiating memory
access.

The completeAcc() part of the instruction should then be
responsible for setting the condition register flags or
updating the base register based on the outcome of the
memory access. This fixes the following instructions:
  * Load Byte and Zero with Update (lbzu)
  * Load Halfword and Zero with Update (lhzu)
  * Load Halfword Algebraic with Update (lhau)
  * Load Word and Zero with Update (lwzu)
  * Load Doubleword with Update (ldu)
  * Load Floating Single with Update (lfsu)
  * Load Floating Double with Update (lfdu)
  * Load Byte and Zero with Update Indexed (lbzux)
  * Load Halfword and Zero with Update Indexed (lhzux)
  * Load Halfword Algebraic with Update Indexed (lhaux)
  * Load Word and Zero with Update Indexed (lwzux)
  * Load Word Algebraic with Update Indexed (lwaux)
  * Load Doubleword with Update Indexed (ldux)
  * Load Floating Single with Update Indexed (lfsux)
  * Load Floating Double with Update Indexed (lfdux)
  * Load Byte And Reserve Indexed (lbarx)
  * Load Halfword And Reserve Indexed (lharx)
  * Load Word And Reserve Indexed (lwarx)
  * Load Doubleword And Reserve Indexed (ldarx)
  * Store Byte with Update (stbu)
  * Store Halfword with Update (sthu)
  * Store Word with Update (stwu)
  * Store Doubleword with Update (stdu)
  * Store Byte with Update Indexed (stbux)
  * Store Halfword with Update Indexed (sthux)
  * Store Word with Update Indexed (stwux)
  * Store Doubleword with Update Indexed (stdux)
  * Store Byte Conditional Indexed (stbcx.)
  * Store Halfword Conditional Indexed (sthcx.)
  * Store Word Conditional Indexed (stwcx.)
  * Store Doubleword Conditional Indexed (stdcx.)
  * Store Floating Single with Update (stfsu)
  * Store Floating Double with Update (stdsu)
  * Store Floating Single with Update Indexed (stfsux)
  * Store Floating Double with Update Indexed (stfdux)

Change-Id: If5f720619ec3c40a90c1362a9dfc8cc204e57acf
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add multi-mode debugging support
Sandipan Das [Sat, 6 Feb 2021 12:20:49 +0000 (17:50 +0530)]
arch-power: Add multi-mode debugging support

This adds multi-mode support for remote debugging via GDB
with the addition of the XML target description files for
both 32-bit and 64-bit variants of the Power architecture.
Proper byte order conversions have also been added.

Since, MSR has now been modeled to some extent, it is also
exposed by getRegs() but setRegs() does not modify it.
Similarly, the target descriptions require FPSCR to also
be part of the payload and hence, it has been added too.

Change-Id: I156fdccb791f161959dbb2c3dd8ab1e510d9cd4b
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Fix process initialization
Sandipan Das [Sat, 6 Feb 2021 12:09:59 +0000 (17:39 +0530)]
arch-power: Fix process initialization

During process initialization, special purpose registers,
represented as misc registers, should either be explicitly
set or cleared. These contain flag bits which might have
unforseen side effects on the execution of a program.

Change-Id: If7c5af9a93283a53717cc8cbba4bf373a7e40560
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add multi-mode support
Sandipan Das [Sat, 6 Feb 2021 12:09:51 +0000 (17:39 +0530)]
arch-power: Add multi-mode support

This adds multi-mode support and allows the simulator to
read, interpret and execute 32bit and 64-bit, big and
little endian binaries in syscall emulation mode.

During process initialization, a minimal set of hardware
capabilities are also advertised by the simulator to show
support for 64-bit mode and little endian byte order.
This also adds some fixups specific to 64-bit ELF ABI v1
that readjust the entry point and symbol table due to the
use of function descriptors.

Change-Id: I124339eff7b70dbd14e50ff970340c88c13bd0ad
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add MSR and associated dependencies
Sandipan Das [Sat, 6 Feb 2021 11:57:58 +0000 (17:27 +0530)]
arch-power: Add MSR and associated dependencies

This adds the definition of the Machine State Register
(MSR) in preparation for multi-mode support. The MSR
has bits that define the state of the processor. This
defines all the bitfields and sets the ones that are
typically used for userspace environments.

In preparation for multi-mode support, the SF and LE
bits are used by instructions to check if the simulation
is running in 64-bit mode and if memory accesses are to
be performed in little endian byte order respectively.
This introduces changes in areas such as target address
computation for branch instructions, carry and overflow
computation for arithmetic instructions, etc.

Change-Id: If9ac69415ca85b0c873bd8579e7d1bd2219eac62
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add hardware features
Sandipan Das [Sat, 6 Feb 2021 11:57:53 +0000 (17:27 +0530)]
arch-power: Add hardware features

This adds definitions for the hardware feature bits that
are currently available from the AT_HWCAP and AT_HWCAP2
auxv entries for the Power architecture. These are being
defined for future use.

Change-Id: I8214a4a26c502b1b0f31837069084b2e7cb31c51
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Refactor process initialization
Sandipan Das [Sat, 6 Feb 2021 11:57:40 +0000 (17:27 +0530)]
arch-power: Refactor process initialization

This generalizes parts of the process initialization
routines in preparation for multi-mode support and
adds flexibility in terms of data types and byte order
used for setting up the environment corresponding to
the mode in use.

Change-Id: Ia9efb93d044682af8b0f0809bca64a17570bf197
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add byte order attribute for PC state
Sandipan Das [Sat, 6 Feb 2021 11:57:36 +0000 (17:27 +0530)]
arch-power: Add byte order attribute for PC state

This adds byte order as an attribute for PC state by
introducing a new PCState class. The decoder can now
fetch instructions bytes in the specified byte order
in preparation for multi-mode support.

Change-Id: I917333df88114a733cc5a8077cc420d5328f608b
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agobase: Add byte order attribute for object files
Sandipan Das [Sat, 6 Feb 2021 11:57:32 +0000 (17:27 +0530)]
base: Add byte order attribute for object files

This adds byte order as an attribute for object files by
introducing new members to the ObjectFile class. This is
populated by the looking at the ELF headers.

Change-Id: Ibe55699175cc0295e0c9d49bdbe02e580988bc4f
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Refactor argument registers
Sandipan Das [Sun, 14 Jun 2020 11:32:00 +0000 (17:02 +0530)]
arch-power: Refactor argument registers

This reintroduces the argument register constants that
were removed in commit 7bb456f02 ("arch-power: Delete
unused register related constants"), adds a definition
for the sixth argument register and switches to these
constants to specify the arguments used by the system
call ABI.

Change-Id: I5804f4d2b27a04d0e7b69132e5abce5761b239f5
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add time base instructions
Sandipan Das [Sat, 6 Feb 2021 11:52:27 +0000 (17:22 +0530)]
arch-power: Add time base instructions

This models a pseudo time base using the simulator ticks
and adds the following instructions.
  * Move From Time Base (mftb)
  * Move From Time Base Upper (mftbu)

Change-Id: Idb619ec3179b2a85925998282075bde8651c68c2
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add move condition field instructions
Sandipan Das [Sat, 6 Feb 2021 11:52:23 +0000 (17:22 +0530)]
arch-power: Add move condition field instructions

This adds the following instructions.
  * Move to CR from XER Extended (mcrxrx)
  * Move To One Condition Register Field (mtocrf)
  * Move From One Condition Register Field (mfocrf)

Change-Id: I5014160d77b1b759c1cb8cba34e6dd20eb2b5205
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Fix move condition field instructions
Sandipan Das [Sat, 6 Feb 2021 11:52:19 +0000 (17:22 +0530)]
arch-power: Fix move condition field instructions

This introduces the S field for X form instructions which
is used to specify signed versus unsigned comparison. The
Power ISA does not specify a formal name for the third
1-bit opcode field required for decoding XFX form move to
and from CR field instructions, the S field can be used
to achieve the same as it has the same span and position.
This fixes the following instructions.
  * Move To Condition Register Fields (mtcrf)
  * Move From Condition Register (mfcr)

Change-Id: I8d291f707cd063781f0497f7226bebfc47bd9e63
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add trap instructions
Sandipan Das [Sat, 6 Feb 2021 11:52:15 +0000 (17:22 +0530)]
arch-power: Add trap instructions

This introduces new classes and new formats for D and X
form instructions, the TO field that is used to encode
the trap conditions and adds the following instructions.
  * Trap Word Immediate (twi)
  * Trap Word (tw)
  * Trap Doubleword Immediate (tdi)
  * Trap Doubleword (td)

Change-Id: I029147ef643c2ee6794426e5e90af4d75f22e92e
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add doubleword rotate instructions
Sandipan Das [Sat, 6 Feb 2021 11:52:12 +0000 (17:22 +0530)]
arch-power: Add doubleword rotate instructions

This introduces a new class and a new format for MD and
MDS form instructions where the shift amount, mask begin
and mask end are specified by two fields that must be
concatenated and adds the following instructions.
  * Rotate Left Doubleword Immediate then Clear Left (rldicl[.])
  * Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
  * Rotate Left Doubleword Immediate then Clear (rldic[.])
  * Rotate Left Doubleword then Clear Left (rldcl[.])
  * Rotate Left Doubleword then Clear Right (rldcr[.])
  * Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])

Change-Id: Id7f1f24032242ccfdfda2f1aefd6fe9f0331f610
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add fields for MD and MDS form instructions
Sandipan Das [Sat, 6 Feb 2021 11:52:07 +0000 (17:22 +0530)]
arch-power: Add fields for MD and MDS form instructions

This introduces the extended opcode fields for MD and
MDS form instructions and the mb and me fields which
are concatenated with the MB and ME fields respectively
for specifying mask bounds for doubleword operands.

Change-Id: I2c3366794ed42f5d31ba1d69e360c0ac67c74e06
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Fix disassembly for rotate instructions
Sandipan Das [Sat, 6 Feb 2021 11:52:03 +0000 (17:22 +0530)]
arch-power: Fix disassembly for rotate instructions

This fixes disassembly generated for integer rotate
instructions based on special use cases for which the
Power ISA provides extended mnemonics.

Change-Id: I8c33e7c8128ad62d856ce050df8a91b2dfd52f4c
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Fix rotate instructions
Sandipan Das [Sat, 6 Feb 2021 11:52:00 +0000 (17:22 +0530)]
arch-power: Fix rotate instructions

Now that 64-bit registers are being used, the rotation
operation changes for words. Instead of just rotating
the lower word of the operand, the lower word is first
duplicated in the upper word and then rotated. This
fixes the following instructions.
  * Rotate Left Word Immediate then And with Mask (rlwinm[.])
  * Rotate Left Word then And with Mask (rlwnm[.])
  * Rotate Left Word Immediate then Mask Insert (rlwimi[.])

Change-Id: Ic743bceb8bafff461276984ecc999dedc1f94e9f
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Refactor rotate instructions
Sandipan Das [Sat, 6 Feb 2021 11:51:57 +0000 (17:21 +0530)]
arch-power: Refactor rotate instructions

This renames the mask span fields and the rotate helper
of the base class.

Change-Id: I120006a0c052fcc34eb154a68d4b7f70a464df65
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add doubleword shift instructions
Sandipan Das [Sat, 6 Feb 2021 11:51:54 +0000 (17:21 +0530)]
arch-power: Add doubleword shift instructions

This introduces a new class and a new format for XS form
instructions where the shift amount is specified by two
fields that must be concatenated and adds the following
instructions.
  * Shift Left Doubleword (sld[.])
  * Shift Right Doubleword (srd[.])
  * Shift Right Algebraic Doubleword (srad[.])
  * Shift Right Algebraic Doubleword Immediate (sradi[.])
  * Extend-Sign Word and Shift Left Immediate (extswsli[.])

Change-Id: If51c676009ddafb40f855b66c00eeeffa5d8874c
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add fields for XS form instructions
Sandipan Das [Sat, 6 Feb 2021 11:51:49 +0000 (17:21 +0530)]
arch-power: Add fields for XS form instructions

This introduces the extended opcode field for XS form
instructions and the sh field which is concatenated
with the SH field for specifying a shift amount for
doubleword operands.

Change-Id: I8f7cb3a2fda33b5b0076ffe12ffebeb5ec1c33a6
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Fix disassembly for shift instructions
Sandipan Das [Sat, 6 Feb 2021 11:51:45 +0000 (17:21 +0530)]
arch-power: Fix disassembly for shift instructions

This fixes disassembly generated for integer shift
instructions based on the type of operand used for
the specifying the shift amount.

Change-Id: I4985334e6eaa9c09ce2d4e79b23e1ae7a9cd28c3
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Fix shift instructions
Sandipan Das [Sat, 6 Feb 2021 11:51:41 +0000 (17:21 +0530)]
arch-power: Fix shift instructions

Now that 64-bit registers are being used, the instructions
must use only the lower word of the operand to be shifted.
This fixes the following instructions.
  * Shift Left Word (slw[.])
  * Shift Right Word (srw[.])
  * Shift Right Algebraic Word (sraw[.])
  * Shift Right Algebraic Word Immediate (srawi[.])

Change-Id: Ibc3124b9e3a8660b0ff9d0178218e34bcc028310
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Refactor shift instructions
Sandipan Das [Sat, 6 Feb 2021 11:51:37 +0000 (17:21 +0530)]
arch-power: Refactor shift instructions

This changes the format for integer shift instructions
such that the computation of the carry bit is implicitly
handled rather than including it in the definition of an
instruction.

Change-Id: Ib916597287efd51b2c9e8781209a8019f2fc38e8
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add bit permute instructions
Sandipan Das [Sat, 6 Feb 2021 11:51:34 +0000 (17:21 +0530)]
arch-power: Add bit permute instructions

This adds the following instructions.
  * Bit Permute Doubleword (bpermd)

Change-Id: Iab3cc6729b9d59c95e29b4f1d3e2c0eb48fde917
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add parity instructions
Sandipan Das [Sat, 6 Feb 2021 11:51:30 +0000 (17:21 +0530)]
arch-power: Add parity instructions

This adds the following instructions.
  * Parity Word (prtyw)
  * Parity Doubleword (prtyd)

Change-Id: Ic102d722f1bc8cea4921ddbf9febfa0e7c0f892e
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add population count instructions
Sandipan Das [Sat, 6 Feb 2021 11:51:23 +0000 (17:21 +0530)]
arch-power: Add population count instructions

This adds the following instructions.
  * Population Count Bytes (popcntb)
  * Population Count Words (popcntw)
  * Population Count Doubleword (popcntd)

Change-Id: Id15188482b45552735c1d960418d5d6ba1f2ede8
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add zero count instructions
Sandipan Das [Sat, 6 Feb 2021 11:51:19 +0000 (17:21 +0530)]
arch-power: Add zero count instructions

This introduces new helpers for finding the count of
leading and trailing zero bits in a given value and adds
the following instructions.
  * Count Trailing Zeros Word (cnttzw[.])
  * Count Leading Zeros Doubleword (cntlzd[.])
  * Count Trailing Zeros Doubleword (cnttzd[.])

Change-Id: I69dad34bc2cffb2ac70ecd3dba7301fa1cdcb340
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add sign-extend instructions
Sandipan Das [Sat, 6 Feb 2021 11:51:16 +0000 (17:21 +0530)]
arch-power: Add sign-extend instructions

This adds the following instructions.
  * Extend Sign Word (extsw[.])

Change-Id: Ia15fc69de665399f1c8d52ca00d2f7670d553b48
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Fix disassembly for logical instructions
Sandipan Das [Sat, 6 Feb 2021 11:51:12 +0000 (17:21 +0530)]
arch-power: Fix disassembly for logical instructions

This fixes disassembly generated for integer logical
instructions based on the type of operands and special
use cases for which the Power ISA provides extended
mnemonics.

Change-Id: I6b67569ef413b0b542e35082ca360c9b4262fc5b
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Fix logical instructions
Sandipan Das [Sat, 6 Feb 2021 11:51:08 +0000 (17:21 +0530)]
arch-power: Fix logical instructions

Now that 64-bit registers are being used, the instructions
performing comparisons must use the entire 64 bits of the
register operands. Also, most of these instructions need
to determine the nature of the result if the Rc bit is set.
This fixes the following instructions.
  * AND (and[.])
  * OR (or[.])
  * XOR (xor[.])
  * NAND (nand[.])
  * NOR (nor[.])
  * Equivalent (eqv[.])
  * AND with Complement (andc[.])
  * OR with Complement (orc[.])
  * Extend Sign Byte (extsb[.])
  * Extend Sign Halfword (extsh[.])
  * Count Leading Zeros Word (cntlzw[.])
  * Compare Bytes (cmpb)

Change-Id: Ifecb0779fa6e2062d382f9abf8b2cfaf7cea3c96
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Refactor logical instructions
Sandipan Das [Sat, 6 Feb 2021 11:51:04 +0000 (17:21 +0530)]
arch-power: Refactor logical instructions

This changes the base class for integer logical instructions
and adds a new class that is used to distinguish between
instructions using different operand types, i.e. register or
immediate. The formats have also been updated to make use of
the new base classes.

Change-Id: Id780cdb16405b01e82dcd22dc6e885ee15b716b2
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add character compare instructions
Sandipan Das [Sat, 6 Feb 2021 11:51:00 +0000 (17:21 +0530)]
arch-power: Add character compare instructions

This adds the following instructions.
  * Compare Ranged Byte (cmprb)
  * Compare Equal Byte (cmpeqb)

Change-Id: I12a9135bf302acd741abe27cb557e8e8bba82edc
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Fix disassembly for compare instructions
Sandipan Das [Sat, 6 Feb 2021 11:50:56 +0000 (17:20 +0530)]
arch-power: Fix disassembly for compare instructions

This fixes disassembly generated for integer compare
instructions based on the type of operands, the type of
comparison to be made and the special use cases for which
the Power ISA provides extended mnemonics.

Change-Id: Ia052bef9589cc3ed290400390028398be28c8eff
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Fix compare instructions
Sandipan Das [Sat, 6 Feb 2021 11:49:40 +0000 (17:19 +0530)]
arch-power: Fix compare instructions

Now that 64-bit registers are being used, instead of always
performing a 32-bit comparison, these instructions must use
the L field to determine the type of comparison to be made.
The comparison can either be 32-bit or 64-bit. This fixes
the following instructions.
  * Compare (cmp)
  * Compare Logical (cmpl)
  * Compare Immediate (cmpi)
  * Compare Logical Immediate (cmpli)

Change-Id: Ia7655ffa463214c24e094e01d4188decf6486904
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Refactor compare instructions
Sandipan Das [Sat, 6 Feb 2021 11:49:36 +0000 (17:19 +0530)]
arch-power: Refactor compare instructions

This changes the base class for integer compare instructions
and adds two new classes that are used to distinguish between
instructions using different operand types, i.e. register or
immediate, and comparison types, i.e. signed or unsigned. The
formats have also been updated to make use of the new base
classes.

Change-Id: Ic6feb803b3a22225d90b8712babd42889b67969d
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add fields for D and X form instructions
Sandipan Das [Sat, 6 Feb 2021 11:49:32 +0000 (17:19 +0530)]
arch-power: Add fields for D and X form instructions

This adds the L field for D and X form instructions that
specifies if a compare instruction should perform 32-bit
or 64-bit comparison of its operands.

Change-Id: I72413a507c93096b1573836197837227c1c1e521
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add doubleword modulo instructions
Sandipan Das [Sat, 6 Feb 2021 11:48:12 +0000 (17:18 +0530)]
arch-power: Add doubleword modulo instructions

This adds the following instructions.
  * Modulo Signed Doubleword (modsd)
  * Modulo Unsigned Doubleword (modud)

Change-Id: Ic7bcb85869ccedf5c95aadfe925c85b3b1155031
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add word modulo instructions
Sandipan Das [Sat, 6 Feb 2021 11:48:08 +0000 (17:18 +0530)]
arch-power: Add word modulo instructions

This adds the following instructions.
  * Modulo Signed Word (modsw)
  * Modulo Unsigned Word (moduw)

Change-Id: Id84ff46d0114ab859bd8616d3dcf22111cf3bda2
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add doubleword divide-extended instructions
Sandipan Das [Sat, 6 Feb 2021 11:48:05 +0000 (17:18 +0530)]
arch-power: Add doubleword divide-extended instructions

This introduces 128-bit division helpers for adds the
following instructions.
  * Divide Doubleword Extended (divde[o][.])
  * Divide Doubleword Extended Unsigned (divdeu[o][.])

Change-Id: I3591d91f22df2dce74fed5147d5de2ce82a83642
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add doubleword divide instructions
Sandipan Das [Sat, 6 Feb 2021 11:48:00 +0000 (17:18 +0530)]
arch-power: Add doubleword divide instructions

This adds the following instructions.
  * Divide Doubleword (divd[o][.])
  * Divide Doubleword Unsigned (divdu[o][.])

Change-Id: Id233a860fcb4b47c8397163a500c783f37be5dd4
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add word divide-extended instructions
Sandipan Das [Sat, 6 Feb 2021 11:47:57 +0000 (17:17 +0530)]
arch-power: Add word divide-extended instructions

This adds the following instructions.
  * Divide Word Extended (divwe[o][.])
  * Divide Word Extended Unsigned (divweu[o][.])

Change-Id: Ie399269938c8e120ece667ce3fc9c6fe1d74faca
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add doubleword multiply-add instructions
Sandipan Das [Sat, 6 Feb 2021 11:47:53 +0000 (17:17 +0530)]
arch-power: Add doubleword multiply-add instructions

This introduces 128-bit addition helpers and adds the
following instructions.
  * Multiply-Add Low Doubleword (maddld)
  * Multiply-Add High Doubleword (maddhd)
  * Multiply-Add High Doubleword Unsigned (maddhdu)

Change-Id: I04e6ea5fb4978b341a6e648424de2930ad41f449
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add fields for VA form instructions
Sandipan Das [Sat, 6 Feb 2021 11:47:49 +0000 (17:17 +0530)]
arch-power: Add fields for VA form instructions

This introduces the extended opcode field for VA form
instructions and the RC field that specifes a GPR to
be used as a register operand.

Change-Id: Ibc63b7392cb552613c755463fb34f2ee2362b2b6
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add doubleword multiply instructions
Sandipan Das [Sat, 6 Feb 2021 11:47:45 +0000 (17:17 +0530)]
arch-power: Add doubleword multiply instructions

This introduces 128-bit multiplication helpers and adds
the following instructions.
  * Multiply Low Doubleword (mulld[o][.])
  * Multiply High Doubleword (mulhd[.])
  * Multiply High Doubleword Unsigned (mulhdu[.])

Change-Id: Id579c95468ffe5fe7b5164579ec1dfb18f0b3ab3
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add PC-relative arithmetic instructions
Sandipan Das [Sat, 6 Feb 2021 11:47:42 +0000 (17:17 +0530)]
arch-power: Add PC-relative arithmetic instructions

This adds the following instructions.
  * Add PC Immediate Shifted (addpcis)

Change-Id: Ib88b8e123ffb328e6f692e0fddb237e420ce38a7
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add fields for DX form instructions
Sandipan Das [Sat, 6 Feb 2021 11:47:38 +0000 (17:17 +0530)]
arch-power: Add fields for DX form instructions

This introduces the extended opcode field for DS form
instructions and the fields d0, d1 and d2 which are
concatenated for specifying a signed integer immediate
operand.

Change-Id: Id60e85d79f9157d680f813bf90ab6e1e064253a9
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Fix disassembly for arithmetic instructions
Sandipan Das [Sat, 6 Feb 2021 11:47:34 +0000 (17:17 +0530)]
arch-power: Fix disassembly for arithmetic instructions

This fixes disassembly generated for integer add and subtract
arithmetic instructions based on the type of operands and the
special use cases for which the Power ISA provides extended
mnemonics.

Change-Id: I89b8271994e4d4b7b16efad170af5eeb5ee1aa10
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Fix arithmetic instructions
Sandipan Das [Sat, 6 Feb 2021 11:47:31 +0000 (17:17 +0530)]
arch-power: Fix arithmetic instructions

The latest Power ISA introduces two new bits that record
carry and overflow out of bit 31 of the result, namely
CA32 and OV32 respectively, thereby changing the behaviour
of the add and subtract instructions that set them. Also,
now that 64-bit registers are being used, the nature of
the result, i.e. less than, greater than or equal to zero,
must be set by a 64-bit signed comparison of the result
to zero. This fixes the following instructions.
  * Add Immediate (addi)
  * Add Immediate Shifted (addis)
  * Add (add[o][.])
  * Subtract From (subf[o][.])
  * Add Immediate Carrying (addic)
  * Add Immediate Carrying and Record (addic.)
  * Subtract From Immediate Carrying (subfic)
  * Add Carrying (addc[o][.])
  * Subtract From Carrying (subfc[o][.])
  * Add Extended (adde[o][.])
  * Subtract From Extended (subfe[o][.])
  * Add to Zero Extended (addze[o][.])
  * Subtract From Zero Extended (subfze[o][.])
  * Negate (neg[o][.])
  * Multiply Low Immediate (mulli)
  * Multiply Low Word (mullw[o][.])
  * Multiply High Word (mulhw[.])
  * Multiply High Word Unsigned (mulhwu[.])
  * Divide Word (divw[o][.])
  * Divide Word Unsigned (divwu[o][.])

Change-Id: I8c79f1dca8b19010ed7b734d7ec9bb598df428c3
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Refactor arithmetic instructions
Sandipan Das [Sat, 6 Feb 2021 11:47:28 +0000 (17:17 +0530)]
arch-power: Refactor arithmetic instructions

This changes the base classes for integer arithmetic
instructions and introduces two new classes that are used
to distinguish between instructions using register and
immediate operands.

Decoding has also been consolidated using formats that can
generate code after determining if an instruction records
carry and overflow and also if it records the nature of the
result, i.e. lesser than, greater than or equal to zero.
However, for multiply and divide instructions, the code to
determine if an overflow has occurred has been moved to the
instruction definition itself. The formats have also been
updated to make use of the new base classes.

Change-Id: I23d70ac4bad4d25d876308db0b3564c092bf574c
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add atomic load-store instructions
Sandipan Das [Sat, 6 Feb 2021 11:47:23 +0000 (17:17 +0530)]
arch-power: Add atomic load-store instructions

This adds the following instructions.
  * Load Byte And Reserve Indexed (lbarx)
  * Load Halfword And Reserve Indexed (lharx)
  * Load Doubleword And Reserve Indexed (ldarx)
  * Store Byte Conditional Indexed (stbcx.)
  * Store Halfword Conditional Indexed (sthcx.)
  * Store Doubleword Conditional Indexed (stdcx.)

Change-Id: Ie85d57e7e111f06dd0f17f9f4d0953be44ef5fb8
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add byte-reversed load-store instructions
Sandipan Das [Sat, 6 Feb 2021 11:47:19 +0000 (17:17 +0530)]
arch-power: Add byte-reversed load-store instructions

This adds the following instructions.
  * Load Halfword Byte-Reverse Indexed (lhbrx)
  * Load Word Byte-Reverse Indexed (lwbrx)
  * Load Doubleword Byte-Reverse Indexed (ldbrx)
  * Store Halfword Byte-Reverse Indexed (sthbrx)
  * Store Word Byte-Reverse Indexed (stwbrx)
  * Store Doubleword Byte-Reverse Indexed (stdbrx)

Change-Id: Id7aae44c370d6376410ab8c82839b908ea6ca196
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add doubleword load-store instructions
Sandipan Das [Sat, 6 Feb 2021 11:47:16 +0000 (17:17 +0530)]
arch-power: Add doubleword load-store instructions

This introduces new formats for DS form instructions and
adds the following instructions.
  * Load Doubleword (ld)
  * Load Doubleword Indexed (ldx)
  * Load Doubleword with Update (ldu)
  * Load Doubleword with Update Indexed (ldux)
  * Store Doubleword (std)
  * Store Doubleword Indexed (stdx)
  * Store Doubleword with Update (stdu)
  * Store Doubleword with Update Indexed (stdux)

Change-Id: I2a88364e82a11685e081f57be5fd5afd44335668
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Fix disassembly for load-store instructions
Sandipan Das [Sat, 6 Feb 2021 11:47:12 +0000 (17:17 +0530)]
arch-power: Fix disassembly for load-store instructions

This fixes disassembly generated for load-store instructions
based on how the base classess that are used to distinguish
between the types of operands used by these instructions.

Change-Id: I5a0f8644cdc6fec934475536861ad342c0a1fb4c
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Fix load-store instructions
Sandipan Das [Sat, 6 Feb 2021 11:47:08 +0000 (17:17 +0530)]
arch-power: Fix load-store instructions

Now that 64-bit registers and operands are being used, the
instructions for words must read or write just one word at
a time. This fixes the following instructions.
  * Load Word and Zero (lwz)
  * Load Word and Zero Indexed (lwzx)
  * Load Word and Zero with Update (lwzu)
  * Load Word and Zero with Update Indexed (lwzux)
  * Load Word And Reserve Indexed (lwarx)
  * Store Word (stw)
  * Store Word Indexed (stwx)
  * Store Word with Update (stwu)
  * Store Word with Update Indexed (stwux)
  * Store Word Conditional Indexed (stwcx.)

This also fixes decoding of load-store update instructions
for some special scenarios when RA is zero or RA and RT
are the same. In such cases, the instruction is considered
invalid.

Change-Id: I6787d3614ba8f1b1cbf30a49f85ef422324d7c21
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Refactor load-store instructions
Sandipan Das [Sat, 6 Feb 2021 11:47:00 +0000 (17:17 +0530)]
arch-power: Refactor load-store instructions

This changes the base classes for load-store instructions
and introduces two new classes for DS form instructions
which use a shifted signed immediate field as the offset
from the base address and for X form instructions which
use registers for both the offset and the base address.
The formats have also been updated to make use of the new
base classes.

Change-Id: Ib5d1bb5d7747813e0e5b1e3075489f1a3aa72660
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add fields for DS form instructions
Sandipan Das [Sat, 6 Feb 2021 11:46:57 +0000 (17:16 +0530)]
arch-power: Add fields for DS form instructions

This introduces the DS field used by DS form instructions
which specifies a signed integer immediate operand.

Change-Id: I0e7a77e7a63fce4e50b7941850c277f556e65724
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Fix precedence of register operands
Sandipan Das [Sat, 6 Feb 2021 11:46:54 +0000 (17:16 +0530)]
arch-power: Fix precedence of register operands

When RS and RA are both used as operands by an instruction,
RS takes precedence over RA. In such cases, either both the
register operands are used as sources or RS is a source and
RA is a destination.

This changes the order by giving RS the highest precedence
and will be useful for proper disassembly generation.

Change-Id: If351a03a814653f2f371afa936ec7a5cd4377b3a
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add TAR and associated instructions
Sandipan Das [Sat, 6 Feb 2021 11:46:50 +0000 (17:16 +0530)]
arch-power: Add TAR and associated instructions

This adds the definition of the Target Address Register (TAR)
and the following instructions that are associated with it.
  * Move To Target Address Register (mttar)
  * Move From Target Address Register (mftar)
  * Branch Conditional to Branch Target Address Register (bctar[l])

Change-Id: I30f54ebd38b503fb6c9ba9dd74d00ccbbc0f8318
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Fix disassembly for branch instructions
Sandipan Das [Sat, 6 Feb 2021 11:46:46 +0000 (17:16 +0530)]
arch-power: Fix disassembly for branch instructions

This fixes disassembly generated for branch instructions
based on the AA and LK bits which determine how the target
address is calculated and whether a return address needs
to be set implicitly or not.

Change-Id: I1acba72c360a1fcb4691de17fbae1a012a752dbe
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Fix branch conditional instructions
Sandipan Das [Sat, 6 Feb 2021 11:46:43 +0000 (17:16 +0530)]
arch-power: Fix branch conditional instructions

Among the register-based conditional branch instructions,
the ones using CTR should not decrement CTR when the bit
corresponding to this action is set in the BO field of
the instruction. In this case, the instruction should be
considered invalid. This fixes the following instructions.
  * Branch Conditional to Count Register (bcctr[l])

Change-Id: Ib2dbf2bc36fced580b4b7f7b76783f68361f6bbf
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Refactor branch instructions
Sandipan Das [Sat, 6 Feb 2021 11:46:39 +0000 (17:16 +0530)]
arch-power: Refactor branch instructions

This changes the base classes for branch instructions and
switches to two high-level classes for unconditional and
conditional branches. The conditional branches are further
classified based on whether they use an immediate field or
a register for determining the target address.

Decoding has also been consolidated using formats that can
generate code after determining if an instruction branches
to an absolute address or a PC-relative address, or if it
implicitly sets the return address by looking at the AA and
LK bits.

Change-Id: I5fa7db7b6693586b4ea3c71e5cad8a60753de29c
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Fix extended opcode based decoding
Sandipan Das [Sat, 6 Feb 2021 11:46:35 +0000 (17:16 +0530)]
arch-power: Fix extended opcode based decoding

When multiple instructions share the same primary opcode,
they are distinguished by the decoder by looking at the
extended opcode. However, the length and position of the
extended opcode field can vary based on instruction form.

This ensures that the correct extended opcode fields are
used for decoding such instructions.

Change-Id: I8207568ac975587377abba8a9b221ca3097b8488
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Add and rename some opcode fields
Sandipan Das [Sat, 6 Feb 2021 11:46:30 +0000 (17:16 +0530)]
arch-power: Add and rename some opcode fields

This introduces separate extended opcode (XO) fields for DS,
X, XFL, XFX, XL and XO form instructions and renames the
primary opcode field to PO based on the convention used in
the Power ISA manual.

Change-Id: I82598efe74c02960f38fe4ed5e22599340f7e15c
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Refactor instruction decoding
Sandipan Das [Sat, 6 Feb 2021 11:46:25 +0000 (17:16 +0530)]
arch-power: Refactor instruction decoding

This reorders the decoding logic based on the category of
instructions. The ordering scheme used here is roughly in
line with the Power ISA manual as shown below.
  * Branch facility instructions
      * Branch instructions
      * Condition Register instructions
      * System Call instructions
  * Fixed-point facility instructions
      * Load instructions
      * Store instructions
      * Arithmetic instructions
      * Compare instructions
      * Logical instructions
      * Rotate and Shift instructions
      * Move To/From System Register instructions
  * Floating-point facility instructions
      * Load instructions
      * Store instructions
      * Arithmetic instructions
      * Move instructions
      * Rounding and Conversion instructions
      * Compare instructions
      * Status and Control Register instructions

Change-Id: Ia2d457967bfebb7b20163b56db1cbbe03ac17ceb
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Refactor special purpose registers
Sandipan Das [Sat, 6 Feb 2021 11:42:50 +0000 (17:12 +0530)]
arch-power: Refactor special purpose registers

This converts the definitions of all the currently defined
Special Purpose Registers (SPRs) to miscellaneous registers
which allows us to print the corresponding SPR name in the
debug logs rather than an ambiguous register number making
things much easier to correlate.

Change-Id: I03f10e3a44a8437beec453dfae2207d71ce43c1e
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agoarch-power: Use 64-bit registers and operands
Sandipan Das [Sat, 6 Feb 2021 11:42:32 +0000 (17:12 +0530)]
arch-power: Use 64-bit registers and operands

This increases the width of the general-purpose registers
and some of the special purpose registers to 64 bits in
accordance with the newer versions of the Power ISA and
enables usage in both 32-bit and 64-bit execution modes.
In 32-bit mode, the use of upper word is dependent on the
instruction being executed and in some cases this may be
undefined.

Change-Id: I2a5865a66e4ceab45e42a833d425abdd6bd6bf55
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
7 months agobase: Add enum to_number tests
Daniel R. Carvalho [Fri, 12 Feb 2021 14:55:46 +0000 (11:55 -0300)]
base: Add enum to_number tests

Add a test to convert a string containing a number into enums.

One of the tests has been disabled to highlight an error-prone
situation where a number that is not a valid enum manages to
be converted to an enum.

Change-Id: I7967c62feea335f3ffda40d8bf0334c20b53ee6c
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41334
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

7 months agoscons: Work around a scons bug when calling TryCompile.
Gabe Black [Fri, 12 Feb 2021 01:42:36 +0000 (17:42 -0800)]
scons: Work around a scons bug when calling TryCompile.

When calling TryCompile with an empty string for the source, useful
when just testing a build flag, some versions of SCons will apparently
create some sort of equivalence between Value('') and Value(0). That
shows itself when creating config file headers, where Value(0) is
switched with Value(''), and the header defines a macro with which
expands to nothing rather than a macro which expands to 0. Later uses
of the macro of the form:

 #if CONFIG_VARIABLE

fail because CONFIG_VARIABLE expands to nothing. If it expanded to 0
like it's supposed to, then the guarded block of code would be excluded
correctly.

Change-Id: Ie324ec5f8dd307c65745b9326a11230e10caa0bd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41213
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
7 months agoarch-x86: Use popCount from bitfields.hh.
Gabe Black [Sat, 13 Feb 2021 01:25:24 +0000 (17:25 -0800)]
arch-x86: Use popCount from bitfields.hh.

Use popCount from bitfields.hh rather than call __builtin_popcountl
directly. That will ensure the instruction works whether or not that
builtin is available.

Change-Id: I947b35bb832b768936b489a58ee324adb8a90b5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41354
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
7 months agoarch: Stop including unnecessary FP headers.
Gabe Black [Sat, 13 Feb 2021 00:56:55 +0000 (16:56 -0800)]
arch: Stop including unnecessary FP headers.

Nothing is used from them. They're probably there as copy/paste from
other ISAs, or old code that's been replaced. This also gets rid of some
 #if guarded includes which is a nice cleanup.

Change-Id: Icd84300fb7531ec203ce4acbdae1d311e56cc873
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41353
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
7 months agomem-ruby: intToTick helper
Tiago Mück [Tue, 18 Aug 2020 21:12:53 +0000 (16:12 -0500)]
mem-ruby: intToTick helper

Change-Id: I76635228223e9a83eef94a25d166d091315a5e96
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41156
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
7 months agomem-ruby: add wakeup_port statement
Tiago Mück [Fri, 28 Aug 2020 01:05:48 +0000 (20:05 -0500)]
mem-ruby: add wakeup_port statement

While the wakeUpBuffers/wakeUpAllBuffers check all message buffers,
wakeup_port wakes up only the messages stalled on the specified port
and address. Usage is the same as the stall_and_wait statement, e.g.:

wakeup_port(reqInPort, addr);

Change-Id: I57dc77d574c0016ca55786ce16a73061a1d37f2e
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41155
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
7 months agomem-ruby: add andMask to WriteMask
Tiago Mück [Tue, 29 Sep 2020 00:15:33 +0000 (19:15 -0500)]
mem-ruby: add andMask to WriteMask

Change-Id: Ieeb68b405a68226077a2ffee231408f554e758a5
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41154
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
7 months agopython: more readable Ruby dot topology
Tiago Mück [Thu, 12 Sep 2019 19:57:44 +0000 (14:57 -0500)]
python: more readable Ruby dot topology

Controllers may have the same name under different parents, thus
the controller full path is used as label. To avoid long and redundant
labels, common prefixes and suffixes are removed from the path.

Change-Id: Id793b59a4c38f3425ae5348138ae1d74c823edd7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41093
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
7 months agoarch-gcn3: Fix sign extension for branches with multiplied offset
Kyle Roarty [Wed, 10 Feb 2021 01:26:21 +0000 (19:26 -0600)]
arch-gcn3: Fix sign extension for branches with multiplied offset

Certain branch instructions specify that the result of (simm16 * 4)
gets sign-extended before being added to the PC.

Previously, that result was being sign extended as if it was still a
16-bit number. This patch fixes that by having the result be sign
extended as an 18-bit number.

Change-Id: Id4d430f8daa71ca7910b570e7e39790626f1decf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41053
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
7 months agoscons: Simplify kvm architecture compatibility check.
Gabe Black [Sun, 7 Feb 2021 11:45:11 +0000 (03:45 -0800)]
scons: Simplify kvm architecture compatibility check.

The original implementation had a function we'd call back into later
which checked if a given ISA has KVM support on the current host.
Instead, this change reverse that and statically figures out which
single target ISA could possibly run under KVM on this host. Then later,
we can just check if the ISA we're trying to build is that one.

Change-Id: I3e7e06180983dfcc4611181718eb5d6210844d36
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40870
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
7 months agoscons: Merge redundant checks for the socket library.
Gabe Black [Sun, 7 Feb 2021 11:29:38 +0000 (03:29 -0800)]
scons: Merge redundant checks for the socket library.

scons can accept more than one library at a time, so lets check for both
at once instead of writing out almost the same check twice.

Change-Id: I82f9bdf59a349e28ca75a615d711051256ec73a4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40869
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
7 months agoscons: Simplify the check for protoc.
Gabe Black [Sun, 7 Feb 2021 11:17:21 +0000 (03:17 -0800)]
scons: Simplify the check for protoc.

Collapse nesting, and constrain the try/except to only the line in that
section which might actually be expected to throw an exception when
things are working normally.

This makes the code easier to read, and won't absorb and discard
exceptions which are thrown for unexpected reasons.

Change-Id: Id3ac417ab5545bef35ed8a87d05211c8ef2f5a50
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40867
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
7 months agoscons: Create a Configure checker for pkg-config.
Gabe Black [Sun, 7 Feb 2021 10:58:47 +0000 (02:58 -0800)]
scons: Create a Configure checker for pkg-config.

This will check if a pkg-config package exists at all, and then if it
does will attempt to use the supplied pkg-config arguments and
ParseConfig to set up the environment as needed.

Change-Id: I1495e5370b60dcebb1c9ce38517e84d727abc2fd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40866
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
7 months agoscons: Simplify the check for hdf5 support.
Gabe Black [Sun, 7 Feb 2021 10:32:01 +0000 (02:32 -0800)]
scons: Simplify the check for hdf5 support.

Collapse the check_hdf5 to the only place it was called, to set a simple
flag variable. Pull the invariant have_pkg_config check out of
check_hdf5_pkg, since if we don't have pkg-config there's no reason to
even try to use to set up hdf5. Turn the one-off, non-standard "Warning"
print into an actual warning().

Change-Id: I04793ae862aeaf1605467d205837b9dd744f93cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40865
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
7 months agoscons: Simplify backtrace implementation detection.
Gabe Black [Sun, 7 Feb 2021 10:13:31 +0000 (02:13 -0800)]
scons: Simplify backtrace implementation detection.

There are really only two options current, glibc or none. If there's a
working implementation there's no real reason to select none, and if
there isn't there's no other option but to select none.

Instead of building up a list, having a default, and making what option
on the list is selected configurable, boil it down to either using glibc
if that implementation is detected, or warning and using none. Also
merge the "normal" and *BSD versions of the checks to reduce redundancy.

The complexity can be added back in if/when there are other
implementations to choose from.

Change-Id: I27c77996a00018302f4daea40924cf059d5a4323
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40864
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
7 months agoscons: Simplify check for have_posix_clock.
Gabe Black [Sun, 7 Feb 2021 09:57:35 +0000 (01:57 -0800)]
scons: Simplify check for have_posix_clock.

The "library" argument can actually be a list, in which case each
element of the list is checked, one after the other. Use that rather
than calling the CheckLibWithHeader method multiple times and manually
oring the results.

Change-Id: I5c774be15eaa9a7e52ec3ee5a1bbcc5ef1fa0f41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40863
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
7 months agoscons: Move a displaced have_posix_clock check back where it goes.
Gabe Black [Sun, 7 Feb 2021 09:50:53 +0000 (01:50 -0800)]
scons: Move a displaced have_posix_clock check back where it goes.

This check had been separated from the code handling have_posix_clock by
some intervening code doing something else. Bring the check back
alongside the code setting that variable.

Change-Id: I6acb54fddbb5c41d6c38d4b93e649835a4775fa0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40862
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
7 months agoscons: Use conf to determine if some flags are supported.
Gabe Black [Sun, 7 Feb 2021 09:48:20 +0000 (01:48 -0800)]
scons: Use conf to determine if some flags are supported.

Use conf rather than checking for particular combinations of OS and/or
compiler versions. This *should* be just as correct, and not require
keeping track of what versions of the tools particular flags were added.

Change-Id: Icaa4c273fe89801e2808e6a814ce476700fd6956
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40861
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
7 months agoscons: In Check(Cxx|Link)Flag, only install the flag if it exists.
Gabe Black [Thu, 11 Feb 2021 06:21:06 +0000 (22:21 -0800)]
scons: In Check(Cxx|Link)Flag, only install the flag if it exists.

These functions where correctly returning whether a flag had existed,
and also correctly not installing it if asked not to. Unfortunately if
they *were* asked to install the flag, they ignored whether or not it
had actually existed to begin with.

Change-Id: I2dca0e1a0ddbc182576d48237aeea5452a02c51b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41159
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
7 months agomem-ruby: fix Sequencer latency reporting
Tiago Mück [Thu, 1 Oct 2020 21:45:56 +0000 (16:45 -0500)]
mem-ruby: fix Sequencer latency reporting

Most protocols won't set initialRequestTime, forwardRequestTime, and
firstResponseTime, thus leading to calculated latency being always 0.

Change-Id: Id2c73314a964bf6efb262d40b3df515373023b84
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41114
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
7 months agomem-ruby: fix functional reads in abstract ctrl
Tiago Mück [Tue, 29 Sep 2020 19:07:23 +0000 (14:07 -0500)]
mem-ruby: fix functional reads in abstract ctrl

When calling functionalMemoryRead we need to check the mem req. queue
first as it may have write data not yet forwarded to the memory port.

Change-Id: Id37aa0837a3462d92ae9ac3b45ca756b2c4f7d97
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41153
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
7 months agomem-ruby: fixes for masked writes
Tiago Mück [Fri, 22 Nov 2019 21:34:47 +0000 (15:34 -0600)]
mem-ruby: fixes for masked writes

This adds DataBlock::setData(PacketPtr) to update the block with
packet data. The method uses the packet's writeData to copy the
correct bytes if the request is a masked write.

Change-Id: I9e5f70fed29edcf55fef94a4b145aa838dc60eac
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41134
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
7 months agomem-ruby: warns on masked functional writes
Tiago Mück [Fri, 17 Jul 2020 15:49:31 +0000 (10:49 -0500)]
mem-ruby: warns on masked functional writes

It's not expected to issue masked functional writes or to receive
functional writes to an address with a pending masked write.

Change-Id: Ibc8ba5f642ff72f897e3a50011c0da6d3000b741
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41133
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
7 months agoarch-arm: Fix CPTR_EL2 writes
Giacomo Travaglini [Mon, 25 Jan 2021 13:24:28 +0000 (13:24 +0000)]
arch-arm: Fix CPTR_EL2 writes

* If E2H==1, CPTR_EL2.ZEN bits are not RES0.
* If E2H==1, CPTR_EL2.FPEN bits are not RES0.

Change-Id: Ic82b266975d89056d7c2f55464bd8a0c18a43e03
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39702
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
7 months agomem: Initialize pendingWrites stat of NVMStats
Hoa Nguyen [Wed, 10 Feb 2021 10:52:33 +0000 (02:52 -0800)]
mem: Initialize pendingWrites stat of NVMStats

The initialization for this stat was mistakenly removed here
https://gem5-review.googlesource.com/c/public/gem5/+/39276

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I27b6ddf6d6b925c9787acb07552a8d5acb081c22
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41073
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
7 months agoscons: Pull Configure() to earlier in SConstruct so we can use it more.
Gabe Black [Sun, 7 Feb 2021 09:41:27 +0000 (01:41 -0800)]
scons: Pull Configure() to earlier in SConstruct so we can use it more.

This mechanism lets us check if headers are available, flags are
supported, etc. We should use that more often, rather than checking for
specific versions of tools where problematic new warnings were added, etc.

Change-Id: I5b1a6499147f27cc8944fcb8c61eb69e9fa8fb7a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40860
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
7 months agobase: Fix copyright of base/stats/SConscript
Daniel R. Carvalho [Fri, 5 Feb 2021 16:36:15 +0000 (13:36 -0300)]
base: Fix copyright of base/stats/SConscript

The original copyright was accidentally removed by
e59557af500d1633b1f41b023d6c072acaf145a0.

Change-Id: Ib3b7a34ea889fbd9a6f2a8e21a6bb24432939da9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40755
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
7 months agoscons: Extract the gem5 specific Configure call to its own file.
Gabe Black [Sun, 7 Feb 2021 08:38:59 +0000 (00:38 -0800)]
scons: Extract the gem5 specific Configure call to its own file.

This modularizes that fairly generic code and pulls it out of the main
SConstruct file.

Change-Id: I5f5edc866af43753b4e0a9cc63774ded0fffe06b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40858
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
7 months agoscons: Trim down a check for mac OS and arch setting flags.
Gabe Black [Sun, 7 Feb 2021 08:20:25 +0000 (00:20 -0800)]
scons: Trim down a check for mac OS and arch setting flags.

This check used uname to determine if scons was running on macos, and
then a fairly elaborate check to see if the version was above 9, and if
the hardware supported 64 bit. I think at this point it's safe to assume
both that we're at least at macos 10 which is 19 years old, and that Mac
hardware supports 64 bit.

Change-Id: Ice66df2530bbcc929d3a37e7679634b75ba7b860
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40857
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>